GQSPI_GEN_FIFO (QSPI) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

GQSPI_GEN_FIFO (QSPI) Register Description

Register NameGQSPI_GEN_FIFO
Offset Address0x0000000140
Absolute Address 0x00FF0F0140 (QSPI)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionGQSPI Generic FIFO Configuration

Software Driver name: XGQSPIPS_GEN_FIFO

GQSPI_GEN_FIFO (QSPI) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:20razRead as zero0x0reserved
GEN_DATA19:0woWrite-only0x0[7:0] Immediate Data Mask
[8] Data Transfer
[9] Exp
[11:10] I/O Mode:
01: SPI
10: Dual SPI
11: Quad SPI
[13:12] Chip Selects
01: Lower CS
10: Upper CS
[15:14] I/O Busses
01: Lower Bus
10: Upper Bus
11: Both Busses
[16] Select TX
[17] Select RX
[18] Select Stripe
[19] Select Poll
Software Driver name: XGQSPIPS_GEN_FIFO_DATA