ATTR_35 (PCIE_ATTRIB) Register Description
| Register Name | ATTR_35 |
|---|---|
| Offset Address | 0x000000008C |
| Absolute Address | 0x00FD48008C (PCIE_ATTRIB) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000001 |
| Description | ATTR_35 |
This register should only be written to during reset of the PCIe block
ATTR_35 (PCIE_ATTRIB) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| attr_link_cap_dll_link_active_reporting_cap | 15 | rwNormal read/write | 0x0 | Data Link Layer Link Active status notification is supported. This is optional for Upstream ports. |
| attr_link_cap_clock_power_management | 14 | rwNormal read/write | 0x0 | Set if the upstream port supports removal of reference clocks in L1 and L23 |
| attr_link_cap_aspm_support | 13:12 | rwNormal read/write | 0x0 | Active State PM Support. Indicates the level of active state power management supported by the selected PCI Express Link, encoded as follows: 0 No ASPM supported, 1 L0s entry supported, 2 Reserved, 3 L0s and L1 entry supported. |
| attr_interrupt_stat_auto | 0 | rwNormal read/write | 0x1 | Causes Interrupt Status to be set if a INTA Assert message is sent via cfg_interrupt*, and to be cleared if a INTA Deassert message is sent. |