Delay (SPI) Register Description
| Register Name | Delay |
|---|---|
| Offset Address | 0x0000000018 |
| Absolute Address |
0x00FF040018 (SPI0) 0x00FF050018 (SPI1) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Clock Delay |
Delay (SPI) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| d_nss | 31:24 | rwNormal read/write | 0x0 | Delay in SPI_REF_CLK for the length that the master mode slave select outputs are de-asserted between words when CPHA = 0. Change only when controller is not actively transmitting or receiving data. |
| d_btwn | 23:16 | rwNormal read/write | 0x0 | Delay in SPI_REF_CLK cycles between one chip select being de-activated and the activation of another. Change only when controller is not actively transmitting or receiving data. |
| d_after | 15:8 | rwNormal read/write | 0x0 | Delay in SPI_REF_CLK cycles from last bit of current word and the first bit of the next word. Change only when controller is not actively transmitting or receiving data. |
| d_int | 7:0 | rwNormal read/write | 0x0 | Added delay in SPI_REF_CLK cycles between setting SSx_b out low and first bit of transfer. Change only when controller is not actively transmitting or receiving data. |