Clock_Control_1 (TTC) Register Description
| Register Name | Clock_Control_1 |
|---|---|
| Offset Address | 0x0000000000 |
| Absolute Address |
0x00FF110000 (TTC0) 0x00FF120000 (TTC1) 0x00FF130000 (TTC2) 0x00FF140000 (TTC3) |
| Width | 7 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Clock Control register |
Clock_Control_1 (TTC) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Ex_E | 6 | rwNormal read/write | 0x0 | External Clock Edge: when this bit is set and the extend clock is selected, the counter clocks on the negative going edge of the external clock input. |
| C_Src | 5 | rwNormal read/write | 0x0 | Clock Source: when this bit is set the counter uses the external clock input, ext_clk; the default clock source is LPD_LSBUS_CLK. |
| PS_V | 4:1 | rwNormal read/write | 0x0 | Prescale value (N): if prescale is enabled, the count rate is divided by 2^(N+1) |
| PS_En | 0 | rwNormal read/write | 0x0 | Prescale enable: when this bit is set the counter, clock source is prescaled; the default clock source is that defined by C_Src.the default |