PGCR3 (DDR_PHY) Register Description
| Register Name | PGCR3 |
|---|---|
| Offset Address | 0x000000001C |
| Absolute Address | 0x00FD08001C (DDR_PHY) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x050A0080 |
| Description | PHY General Configuration Register 3 |
PGCR3 (DDR_PHY) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| CKNEN | 27:24 | rwNormal read/write | 0x5 | CKN Enable: Controls whether the CKN going to the SDRAM is enabled (toggling) or disabled (static value) and whether the CKN is inverted. Two bits for each of the two CKN pairs. Valid values for the two bits are: 2b00 = CKN disabled (Driven to constant 0) 2b01= CKN toggling with normal polarity (Default setting) 2b10 = CKN toggling with inverted polarity 2b11 = CKN disabled (Driven to constant 1) |
| CKEN | 19:16 | rwNormal read/write | 0xA | CK Enable: Controls whether the CK going to the SDRAM is enabled (toggling) or disabled (static value) and whether the CK is inverted. Two bits for each of the two CK pairs. Valid values for the two bits are: 2b00 = CK disabled (Driven to constant 0) 2b01 = CK toggling with inverted polarity 2b10 = CK toggling with normal polarity (This should be the default setting) 2b11 = CK disabled (Driven to constant 1) |
| Reserved | 15 | roRead-only | 0x0 | Reserved. Return zeroes on reads. |
| GATEACRDCLK | 14:13 | rwNormal read/write | 0x0 | Enable Clock Gating for AC [0] ctl_rd_clk: Enables, when set, clock gating for power saving. Valid values are: 2b00 = Dynamic 2b01 = Always ON 2b10 = Always OFF 2b11 = Reserved |
| GATEACDDRCLK | 12:11 | rwNormal read/write | 0x0 | Enable Clock Gating for AC [0]ddr_clk: Enables, when set, clock gating for power saving. Valid values are: 2b00 = Dynamic 2b01 = Always ON 2b10 = Always OFF 2b11 = Reserved |
| GATEACCTLCLK | 10:9 | rwNormal read/write | 0x0 | Enable Clock Gating for AC [0] ctl_clk: Enables, when set, clock gating for power saving. Valid values are: 2b00 = Dynamic 2b01 = Always ON 2b10 = Always OFF 2b11 = Reserved |
| Reserved | 8 | roRead-only | 0x0 | Reserved. Return zeroes on reads. |
| DDLBYPMODE | 7:6 | rwNormal read/write | 0x2 | Controls DDL Bypass Modes. Valid values are: 2b00 = Normal dynamic control 2b01 = All DDLs bypassed 2b10 = No DDLs bypassed 2b11 = Reserved |
| IOLB | 5 | rwNormal read/write | 0x0 | I/O Loop-Back Select: Selects where inside the I/O the loop-back of signals happens. Valid values are: 1b0 = Loopback is after output buffer; output enable must be asserted 1b1 = Loopback is before output buffer; output enable is don't care |
| RDMODE | 4:3 | rwNormal read/write | 0x0 | AC Receive FIFO Read Mode. Valid values are: 2b00 = 2 stage synchronizer async FIFO 2b01 = 3 stage synchronizer async FIFO 2b10 = 4 stage synchronizer async FIFO 2b11 = AC loopback read mode FIFO static read response enabled Note: The static response mode should be selected only when system is in IDLE. The static response mode must be OFF when Initialization, Training, BIST or DCU operation is performed. |
| DISRST | 2 | rwNormal read/write | 0x0 | Disables the Read FIFO reset: When set, read receive FIFO can't be reset from ctl_dx_rdfifo_rstn input. Valid values are: 1b0 = RX Read FIFO is reset when ctl_dx_rxfifo_rstn is LOW. 1b1 = RX Read FIFO can't be reset by ctl_dx_rxfifo_rstn |
| CLKLEVEL | 1:0 | rwNormal read/write | 0x0 | Selects the level to which clocks will be stalled when clock gating is enabled in PHY. Valid values are: 2b00 = Clocks will stall to static level 0 2b01 = Clocks will stall to static level 1 2b10 - 2b11= Clocks will toggle at slow speed. |