GDBGLTSSM (USB3_XHCI) Register Description
| Register Name | GDBGLTSSM |
|---|---|
| Offset Address | 0x000000C164 |
| Absolute Address |
0x00FE20C164 (USB3_0_XHCI) 0x00FE30C164 (USB3_1_XHCI) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x01000442 |
| Description | Global Debug LTSSM Register In multi-port host configuration, the port-number is defined by Port-Select[3:0] field in the GDBGFIFOSPACE register. Note: - GDBGLTSSM register is not applicable for USB 2.0-only mode. - Bit Bash test should not be done on this debug register. |
GDBGLTSSM (USB3_XHCI) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31 | roRead-only | 0x0 | Reserved |
| RxElecidle | 30 | roRead-only | 0 | RxElecidle For description of RxElecIdle, see table 5-4, Status Interface Signals of the PIPE3 Specification. add this as reference https://www.intel.in/content/dam/doc/white-paper/usb3-phy-interface-pci-express-paper.pdf |
| X3_XS_SWAPPING | 29 | roRead-only | 0x0 | a3_ds_swapping/a3_us_swapping/ b3_ds_swapping/b3_us_swapping Interpret this field based on the Port direction. Note: This bit is applicable only for OTG 3.0 mode of operation and is Reserved for other modes. |
| X3_DS_HOST_SHUTDOWN | 28 | roRead-only | 0x0 | a3_ds_host_shutdown/b3_ds_host_shutdown Note: This bit is applicable only for OTG 3.0 mode of operation and is Reserved for other modes. |
| PRTDIRECTION | 27 | roRead-only | 0x0 | Port Direction - 1b0: Upstream - 1b1: Downstream Note: This bit is applicable only for OTG 3.0 mode of operation and is Reserved for other modes. |
| LTDBTIMEOUT | 26 | roRead-only | 0x0 | LTDB Timeout (LTDBTimeout) |
| LTDBLINKSTATE | 25:22 | roRead-only | 0x4 | LTDB Link State (LTDBLinkState) |
| LTDBSUBSTATE | 21:18 | roRead-only | 0x0 | LTDB Sub-State (LTDBSubState) |
| ELASTICBUFFERMODE | 17 | roRead-only | 0x0 | Elastic Buffer Mode (ElasticBufferMode) For field definition, refer to Table 5-3 of the PIPE3 specification.add this as reference https://www.intel.in/content/dam/doc/white-paper/usb3-phy-interface-pci-express-paper.pdf |
| TXELECLDLE | 16 | roRead-only | 0 | Tx Elec Idle (TxElecIdle) For field definition, refer to Table 5-3 of the PIPE3 specification.add this as reference https://www.intel.in/content/dam/doc/white-paper/usb3-phy-interface-pci-express-paper.pdf |
| RXPOLARITY | 15 | roRead-only | 0x0 | Rx Polarity (RxPolarity) For field definition, refer to Table 5-3 of the PIPE3 specification.add this as reference https://www.intel.in/content/dam/doc/white-paper/usb3-phy-interface-pci-express-paper.pdf |
| TxDetRxLoopback | 14 | roRead-only | 0x0 | Tx Detect Rx/Loopback (TxDetRxLoopback) For field definition, refer to Table 5-3 of the PIPE3 specification.add this as reference https://www.intel.in/content/dam/doc/white-paper/usb3-phy-interface-pci-express-paper.pdf |
| LTDBPhyCmdState | 13:11 | roRead-only | 0x0 | LTSSM PHY command State (LTDBPhyCmdState) - 000: PHY_IDLE (PHY command state is in IDLE. No PHY request pending) - 001: PHY_DET (Request to start Receiver detection) - 010: PHY_DET_3 (Wait for Phy_Status (Receiver detection)) - 011: PHY_PWR_DLY (Delay Pipe3_PowerDown P0 -> P1/P2/P3 request) - 100: PHY_PWR_A (Delay for internal logic) - 101: PHY_PWR_B (Wait for Phy_Status(Power state change request)) |
| POWERDOWN | 10:9 | roRead-only | 0x2 | POWERDOWN (PowerDown) For field definition, refer to Table 5-3 of the PIPE3 specification. add this as reference https://www.intel.in/content/dam/doc/white-paper/usb3-phy-interface-pci-express-paper.pdf |
| RXEQTRAIN | 8 | roRead-only | 0x0 | RxEq Train For field definition, refer to Table 5-3 of the PIPE3 specification. add this as reference https://www.intel.in/content/dam/doc/white-paper/usb3-phy-interface-pci-express-paper.pdf |
| TXDEEMPHASIS | 7:6 | roRead-only | 0x1 | TXDEEMPHASIS (TxDeemphasis) For field definition, refer to Table 5-3 of the PIPE3 specification. add this as reference https://www.intel.in/content/dam/doc/white-paper/usb3-phy-interface-pci-express-paper.pdf |
| LTDBClkState | 5:3 | roRead-only | 0x0 | LTSSM Clock State (LTDBClkState) In multi-port host configuration, the port number is defined by Port-Select[3:0] field in the GDBGFIFOSPACE register. Note: GDBGLTSSM register is not applicable for USB 2.0-only mode. - 000: CLK_NORM (PHY is in non-P3 state and PCLK is running) - 001: CLK_TO_P3 (P3 entry request to PHY); - 010: CLK_WAIT1 (Wait for Phy_Status (P3 request)); - 011: CLK_P3 (PHY is in P3 and PCLK is not running); - 100: CLK_TO_P0 (P3 exit request to PHY); - 101: CLK_WAIT2 (Wait for Phy_Status (P3 exit request)) |
| TXSWING | 2 | roRead-only | 0x0 | Tx Swing (TxSwing) For field definition, refer to Table 5-3 of the PIPE3 specification. add this as reference https://www.intel.in/content/dam/doc/white-paper/usb3-phy-interface-pci-express-paper.pdf |
| RXTERMINATION | 1 | roRead-only | 0x1 | Rx Termination (RxTermination) For details on `DWC_USB3_PIPE_RXTERM_RESET_VAL, refer to <workspace>/src/DWC_usb3_params.v |
| TXONESZEROS | 0 | roRead-only | 0x0 | Tx Ones/Zeros (TxOnesZeros) For field definition, refer to Table 5-3 of the PIPE3 specification. add this as reference https://www.intel.in/content/dam/doc/white-paper/usb3-phy-interface-pci-express-paper.pdf |