ACIOCR0 (DDR_PHY) Register Description
| Register Name | ACIOCR0 |
|---|---|
| Offset Address | 0x0000000500 |
| Absolute Address | 0x00FD080500 (DDR_PHY) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x30000000 |
| Description | AC I/O Configuration Register 0 |
ACIOCR0 (DDR_PHY) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| ACSR | 31:30 | rwNormal read/write | 0x0 | Address/Command Slew Rate (D3F I/O Only): Selects slew rate of the I/O for all address and command pins. |
| RSTIOM | 29 | rwNormal read/write | 0x1 | SDRAM Reset I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for SDRAM Reset. |
| RSTPDR | 28 | rwNormal read/write | 0x1 | SDRAM Reset Power Down Receiver: Powers down, when set, the input receiver on the I/O for SDRAM RST# pin. |
| Reserved | 27 | roRead-only | 0x0 | Reserved. Return zeros on reads. |
| RSTODT | 26 | rwNormal read/write | 0x0 | SDRAM Reset On-Die Termination: Enables, when set, the on-die termination on the I/O for SDRAM RST# pin. |
| Reserved | 25:10 | roRead-only | 0x0 | Reserved. Return zeros on reads. |
| CKDCC | 9:6 | rwNormal read/write | 0x0 | CK Duty Cycle Correction |
| ACPDRMODE | 5:4 | rwNormal read/write | 0x0 | AC Power Down Receiver mode for AC CK, CK_N 2b00 = PDR Dynamic 2b01 = PDR always ON 2b10 = PDR always OFF 2b11 = Reserved |
| ACODTMODE | 3:2 | rwNormal read/write | 0x0 | Address/Command On-Die mode for AC, CK, CK_N 2b00 = ODT Dynamic 2b01 = ODT always ON 2b10 = ODT always OFF 2b11 = Reserved |
| Reserved | 1 | roRead-only | 0x0 | Reserved. Return zeros on reads. |
| ACRANKCLKSEL | 0 | rwNormal read/write | 0x0 | Control delayed or non-delayed clock to CS_N/ODT/CKE AC slices. This bit is used in LPDDR4 CBT. 1'b0: Non-delayed clock to CS_N/ODT/CKE AC slices. 1'b1: Delayed clock to CS_N/ODT/CKE AC slices. |