L1_TXPMD_TM_45 (SERDES) Register - L1_TXPMD_TM_45 (SERDES) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID: UG1087
Release Date: 2025-06-20
Revision: 1.11

L1_TXPMD_TM_45 (SERDES) Register Description

Register Name	L1_TXPMD_TM_45
Offset Address	0x0000004CB4
Absolute Address	0x00FD404CB4 (SERDES)
Width	32
Type	mixedMixed types. See bit-field details.
Reset Value	0x00000000
Description	Register value is generated by Vivado PCW.

L1_TXPMD_TM_45 (SERDES) Register Bit-Field Summary

Field Name	Bits	Type	Reset Value	Description
TXPMD_TM_45_31_8_rsvd	31:8	roRead-only	0x0	Value generated by PCW.
ana_dp_byp0_7_6_rsvd	7:6	roRead-only	0x0	Value generated by PCW.
dp_TM_TX_dp_enable_post2_path	5	rwNormal read/write	0x0	Value generated by PCW.
dp_TM_TX_ovrd_dp_enable_post2_path	4	rwNormal read/write	0x0	Value generated by PCW.
dp_TM_TX_dp_enable_post1_path	3	rwNormal read/write	0x0	Value generated by PCW.
dp_TM_TX_ovrd_dp_enable_post1_path	2	rwNormal read/write	0x0	Value generated by PCW.
dp_TM_TX_dp_enable_main_path	1	rwNormal read/write	0x0	Value generated by PCW.
dp_TM_TX_ovrd_dp_enable_main_path	0	rwNormal read/write	0x0	Value generated by PCW.