AXICC (SATA_AHCI_VENDOR) Register Description
| Register Name | AXICC |
|---|
| Offset Address | 0x000000001C |
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| Absolute Address |
0x00FD0C00BC (SATA_AHCI_VENDOR)
|
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| Width | 32 |
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| Type | mixedMixed types. See bit-field details. |
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| Reset Value | 0x00100010 |
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| Description | AXI CACHE Control. |
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Controls the value of the AWCACHE and ARCACHE used to distinguish each address operation on the address bus.
AXICC (SATA_AHCI_VENDOR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|
| Reserved | 31:30 | roRead-only | 0x0 | Reserved |
| EARC | 29 | rwNormal read/write | 0x0 | Enable the ARCACHE (EARC): control from the PRDT entries used during the data phase of this operation (Global Control) |
| AWCF | 27:24 | rwNormal read/write | 0x0 | Address Write Cache FIS (AWCF): This is the value driven onto AWCACHE when the AXI host is posting a status FIS write address to the memory controller |
| AWCD | 23:20 | rwNormal read/write | 0x1 | Address Write Cache Data (AWCD): This is the value driven onto AWCACHE when the AXI master is posting a Data burst write address to the memory controller when the data burst is not the final burst in the transfer. |
| AWCFD | 19:16 | rwNormal read/write | 0x0 | Address Write Cache Final Data (AWCFD): This is the value driven onto AWCACHE when the AXI master is posting a Data burst write address to the memory controller when the data burst is the final burst in the transfer. |
| ARCP | 15:12 | rwNormal read/write | 0x0 | Address Read Cache PRD (ARCP): This is the value driven onto ARCACHE when the AXI master is posting a PRD read address to the memory controller |
| ARCH | 11:8 | rwNormal read/write | 0x0 | Address Read Cache Header (ARCH): This is the value driven onto ARCACHE when the AXI master is posting a Header or physical region descriptor read address to the memory controller |
| ARCF | 7:4 | rwNormal read/write | 0x1 | Address Read Cache FIS (ARCF): This is the value driven onto ARCACHE when the AXI master is posting a command FIS read address to the memory controller |
| ARCA | 3:0 | rwNormal read/write | 0x0 | Address Read Cache ATAPI (ARCA): This is the value driven onto ARCACHE when the AXI master is posting a data burst or ATAPI FIS read address to the memory controller |