ERROR_STATUS_2 (PMU_GLOBAL) Register Description
| Register Name | ERROR_STATUS_2 |
|---|---|
| Offset Address | 0x0000000540 |
| Absolute Address | 0x00FFD80540 (PMU_GLOBAL) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | System Errors; Interrupt Clear and Status, Reg 2. |
Status and clear of System Errors. Read: 0: no error. 1: system error active. Write: 0: no effect. 1: clear the bit to 0. Note: If a Status bit is 1 and its Mask is 0, then the interrupt signal is active to the interrupt controllers. The system errors can be generated by many areas of the PS and PL. For details on bit fields, refer to the ERROR_STATUS_2 register description. Register is reset only by the PS_POR_B reset signal pin.
ERROR_STATUS_2 (PMU_GLOBAL) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:27 | roRead-only | 0x0 | reserved |
| CSU_ROM | 26 | wtcReadable, write a 1 to clear | 0x0 | CSU BootROM Sequence Error. CSU_BR_ERROR [BR_ERROR] bit is set and the [ERR_TYPE] bit field contains the error code. |
| PMU_PB | 25 | wtcReadable, write a 1 to clear | 0x0 | Error occurred during PMU Pre-Boot Sequence; fatal, may indicate a defective device. |
| PMU_SERVICE | 24 | wtcReadable, write a 1 to clear | 0x0 | Request for Services cause error while executing from ROM. |
| Reserved | 23:22 | roRead-only | 0x0 | reserved |
| PMU_FW | 21:18 | wtcReadable, write a 1 to clear | 0x0 | Four (4) Firmware defined error bits. Bits [21:18] can be activated by user firmware. |
| PMU_UC | 17 | wtcReadable, write a 1 to clear | 0x0 | PMU BootROM Error. Includes PMU ROM validation error, PMU Triple Module Redundancy (TMR) error, PMU RAM uncorrectable ECC error, and PMU Local Register address error. |
| CSU | 16 | wtcReadable, write a 1 to clear | 0x0 | CSU hardware generated error including CSU ROM validation error. CSU boot fails, ROM is not executed. |
| Reserved | 15:13 | roRead-only | 0x0 | reserved |
| PLL_LOCK | 12:8 | wtcReadable, write a 1 to clear | 0x0 | PLL Lock Errors. Bit [8] is for IOPLL. Bit [9] is for RPLL. Bit [10] is for APLL. Bit [11] is for DPLL. Bit [12] is for VPLL. |
| Reserved | 7:6 | roRead-only | 0x0 | reserved |
| PL | 5:2 | wtcReadable, write a 1 to clear | 0x0 | PL to PS Signals. Bit [2] is PL System Error Signal. Bit [3] is PL System Error Signal. Bit [4] is PL System Error Signal. Bit [5] is PL System Error Signal. |
| TO | 1:0 | wtcReadable, write a 1 to clear | 0x0 | AXI Timeout Buffer (ATB). Bit [0] is for ATBs in the LPD. Bit [1] is for ATBs in the FPD. The ATB timeout signals within a power domain are ORed together |