L1_TX_ANA_TM_16 (SERDES) Register Description
| Register Name | L1_TX_ANA_TM_16 |
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| Offset Address | 0x0000004040 |
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| Absolute Address |
0x00FD404040 (SERDES)
|
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| Width | 32 |
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| Type | mixedMixed types. See bit-field details. |
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| Reset Value | 0x00000000 |
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| Description | Override for TX margin |
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NOTE: the register descriptions for public registers are not available except in the ODS files.
L1_TX_ANA_TM_16 (SERDES) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|
| TX_ANA_TM_16_31_8_rsvd | 31:8 | roRead-only | 0x0 | Reserved |
| ana_byp16_7_4_rsvd | 7:4 | roRead-only | 0x0 | Reserved |
| pipe_TX_Margin | 3:1 | rwNormal read/write | 0x0 | PIPE TX Margin. As per PIPE3 spec |
| force_pipe_TX_Margin | 0 | rwNormal read/write | 0x0 | Enable/disable test register force for PIPT TX Margin |