| Field Name | Bits | Type | Reset Value | Description |
|---|
| Reserved | 31:8 | razRead as zero | 0x0 | Reserved |
| integ_sec_override | 7 | rwNormal read/write | 0x0 | indicates non-secure transactions can access integration registers |
| cttw | 6 | rwNormal read/write | 0x0 | Indicates if System supports Coherent page table walks |
| sysbardisable_tbu5 | 5 | rwNormal read/write | 0x1 | Enable barrier support for TBU5 |
| sysbardisable_tbu4 | 4 | rwNormal read/write | 0x1 | Enable barrier support for TBU4 |
| sysbardisable_tbu3 | 3 | rwNormal read/write | 0x1 | Enable barrier support for TBU3 |
| sysbardisable_tbu2 | 2 | rwNormal read/write | 0x1 | Enable barrier support for TBU2 |
| sysbardisable_tbu1 | 1 | rwNormal read/write | 0x1 | Enable barrier support for TBU1 |
| sysbardisable_tbu0 | 0 | rwNormal read/write | 0x1 | Enable barrier support for TBU0 |