GP_CONTR_REG_STATUS (GPU) Register Description
| Register Name | GP_CONTR_REG_STATUS |
|---|---|
| Offset Address | 0x0000000068 |
| Absolute Address | 0x00FD4B0068 (GPU) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x00000000 |
| Description | GP Control Register Status |
GP_CONTR_REG_STATUS (GPU) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:10 | roRead-only | 0x0 | Reserved, write as zero, read undefined. |
| CLK_OVERRIDE | 9 | roRead-only | 0x0 | Shows that the block level clock gates have been disabled This bit is set by the GP_CLK_OVERRIDE command in the GP_CONTR_REG_CMD Register. When this bit is set, all the architectural clock gates in the design are overridden so all clocks are always active |
| GP_STATUS_WRITE_BOUND_ERR | 8 | roRead-only | 0x0 | Write boundaries error detected. |
| GP_STATUS_HANG | 7 | roRead-only | 0x0 | Watchdog timer limit reached. This state can also be triggered under normal rendering if you are running a shader where it is near to a never-ending inner loop. From the software perspective, you can ignore this state, because this is merely a hint from the HW that something might be wrong. The SW then decides to either reset the processor, or continue to let it run. |
| GP_STATUS_BUS_ERROR | 6 | roRead-only | 0x0 | Bus error detected. |
| GP_STATUS_PLB_STALLED | 5 | roRead-only | 0x0 | PLB stalled on list allocation. |
| Reserved | 4 | roRead-only | 0x0 | Reserved, write as zero, read undefined. |
| GP_STATUS_PLB_ACTIVE | 3 | roRead-only | 0x0 | PLB active. |
| GP_STATUS_BUS_STOPPED | 2 | roRead-only | 0x0 | Stop command issued. |
| GP_STATUS_VS_ACTIVE | 1 | roRead-only | 0x0 | Vertex shader active. |
| GP_STATUS_IRQ | 0 | roRead-only | 0x0 | IRQ asserted. |