Data_interface_register (NAND) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

Data_interface_register (NAND) Register Description

Register NameData_interface_register
Offset Address0x000000006C
Absolute Address 0x00FF10006C (NAND)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionData Interface Configuration

Data_interface_register (NAND) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:11razRead as zero0x0reserved
data_intf10:9rwNormal read/write0x000: SDR mode is enabled
01: NV-DDR mode is enabled
Note: Change this value only when controller is not communicating with the memory device.
NVDDR 5:3rwNormal read/write0x0000: NV-DDR mode 0
001: NV-DDR mode 1
010: NV-DDR mode 2
011: NV-DDR mode 3
100: NV-DDR mode 4
101: NV-DDR mode 5
110: reserved
Note: Change this value only when controller is not communicating with the memory device.
SDR 2:0rwNormal read/write0x0000: SDR mode 0
001: SDR mode 1
010: SDR mode 2
011: SDR mode 3
100: SDR mode 4
101: SDR mode 5
110: reserved
Note: Change this value only when controller is not communicating with the memory device.