L0_TM_EQ0 (SERDES) Register Description
| Register Name | L0_TM_EQ0 |
|---|---|
| Offset Address | 0x000000194C |
| Absolute Address | 0x00FD40194C (SERDES) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Register value is generated by Vivado PCW. |
L0_TM_EQ0 (SERDES) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| TM_EQ0_31_8_rsvd | 31:8 | roRead-only | 0x0 | Value generated by PCW. |
| eq_stg1_rl_prog_msb | 7 | rwNormal read/write | 0x0 | Value generated by PCW. |
| eq_stg1_ctrl_byp | 6 | rwNormal read/write | 0x0 | Value generated by PCW. |
| eq_stg2_ctrl_byp | 5 | rwNormal read/write | 0x0 | Value generated by PCW. |
| eq_adaptation_force | 4 | rwNormal read/write | 0x0 | Value generated by PCW. |
| eq_adaptation_force_val | 3 | rwNormal read/write | 0x0 | Value generated by PCW. |
| eq_isource_en_val | 2:0 | rwNormal read/write | 0x0 | Value generated by PCW. |