SMMU_SIDR0 (SMMU500) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID: UG1087
Release Date: 2024-03-13
Revision: 1.10

SMMU_SIDR0 (SMMU500) Register Description

Register Name	SMMU_SIDR0
Offset Address	0x0000000020
Absolute Address	0x00FD800020 (SMMU_GPV)
Width	32
Type	roRead-only
Reset Value	0xFC013E30
Description	Provides SMMU capability information.

SMMU_SIDR0 (SMMU500) Register Bit-Field Summary

Field Name	Bits	Type	Reset Value	Description
SES	31	roRead-only	0x1	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
S1TS	30	roRead-only	0x1	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
S2TS	29	roRead-only	0x1	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
NTS	28	roRead-only	0x1	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
SMS	27	roRead-only	0x1	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
ATOSNS	26	roRead-only	0x1	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
PTFS	25:24	roRead-only	0x0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
NUMIRPT	23:16	roRead-only	0x1	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
CTTW	14	roRead-only	0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
BTM	13	roRead-only	0x1	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
NUMSIDB	12:9	roRead-only	0xF	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
NUMSMRG	7:0	roRead-only	0x30	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details