L0_TM_MISC1 (SERDES) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

L0_TM_MISC1 (SERDES) Register Description

Register NameL0_TM_MISC1
Offset Address0x0000001898
Absolute Address 0x00FD401898 (SERDES)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionRegister value is generated by Vivado PCW.

L0_TM_MISC1 (SERDES) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
hsrx_polarity_flip 7rwNormal read/write0x0Value generated by PCW.