PMCNTENCLR (SMMU500) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

PMCNTENCLR (SMMU500) Register Description

Register NamePMCNTENCLR
Offset Address0x0000003C20
Absolute Address 0x00FD803C20 (SMMU_GPV)
Width32
TypewoWrite-only
Reset Value0x00000000
DescriptionPerformance Monitor Counter Enable Clear registers are used to disable the event counters PMEVCNTRxx.

PMCNTENCLR (SMMU500) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
P2323woWrite-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
P2222woWrite-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
P2121woWrite-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
P2020woWrite-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
P1919woWrite-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
P1818woWrite-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
P1717woWrite-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
P1616woWrite-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
P1515woWrite-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
P1414woWrite-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
P1313woWrite-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
P1212woWrite-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
P1111woWrite-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
P1010woWrite-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
P9 9woWrite-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
P8 8woWrite-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
P7 7woWrite-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
P6 6woWrite-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
P5 5woWrite-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
P4 4woWrite-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
P3 3woWrite-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
P2 2woWrite-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
P1 1woWrite-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
P0 0woWrite-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details