SMMU500 Module

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID

UG1087

Release Date

2024-03-13

Revision

1.10

SMMU500 Module Description

Module Name	SMMU500 Module
Modules of this Type	SMMU_GPV
Base Addresses	0x00FD800000 (SMMU_GPV)
Description	FPD System Memory Management Unit (GPV)

SMMU500 Module Register Summary

Register Name	Offset Address	Width	Type	Reset Value	Description
SMMU_SCR0	0x0000000000	32	mixedMixed types. See bit-field details.	0x00200001	Provides top-level control of the SMMU.
SMMU_SCR1	0x0000000004	32	mixedMixed types. See bit-field details.	0x02013010	Provides top-level Secure control of the SMMU.
SMMU_SACR	0x0000000010	32	rwNormal read/write	0x04000004	Provides IMPLEMENTATION DEFINED functionality.
SMMU_SIDR0	0x0000000020	32	roRead-only	0xFC013E30	Provides SMMU capability information.
SMMU_SIDR1	0x0000000024	32	roRead-only	0x30000F10	Provides SMMU capability information.
SMMU_SIDR2	0x0000000028	32	roRead-only	0x00005555	Provides SMMU capability information.
SMMU_SIDR7	0x000000003C	32	roRead-only	0x00000021	Provides SMMU capability information.
SMMU_SGFAR_low	0x0000000040	32	rwNormal read/write	0x00000000	Contains the input address of an erroneous request reported by SMMU_sGFSR.
SMMU_SGFAR_high	0x0000000044	32	rwNormal read/write	0x00000000	Contains the input address of an erroneous request reported by SMMU_sGFSR.
SMMU_SGFSR	0x0000000048	32	woWrite-only	0x00000000	Gives the fault status for each of the following possible faults.
SMMU_SGFSRRESTORE	0x000000004C	32	woWrite-only	0x00000000	Restores the state of SMMU_sGFSR, after a reset, for example.
SMMU_SGFSYNR0	0x0000000050	32	mixedMixed types. See bit-field details.	0x00000000	Contains fault syndrome information relating to SMMU_sGFSR.
SMMU_SGFSYNR1	0x0000000054	32	rwNormal read/write	0x00000000	Contains fault syndrome information relating to SMMU_sGFSR.
SMMU_STLBIALL	0x0000000060	32	woWrite-only	0x00000000	Invalidates all unlocked Secure entries in the TLB.
SMMU_TLBIVMID	0x0000000064	32	woWrite-only	0x00000000	Invalidates all Non-secure non-Hyp TLB entries having the specified VMID.
SMMU_TLBIALLNSNH	0x0000000068	32	woWrite-only	0x00000000	Invalidates all Non-secure non-Hyp tagged entries in the TLB.
SMMU_STLBGSYNC	0x0000000070	32	woWrite-only	0x00000000	Starts a global synchronization operation that ensures the completion of any previously accepted TLB Invalidate operation. As a minimum, the operation applies to the specified security state, and includes all TLB Invalidate operations initiated in context banks associated with that security state.
SMMU_STLBGSTATUS	0x0000000074	32	roRead-only	0x00000000	Gives the status of a TLB maintenance operation.
SMMU_DBGRPTRTBU	0x0000000080	32	rwNormal read/write	0x00000000	Address of TLB entry in a specific TBU.
SMMU_DBGRDATATBU	0x0000000084	32	roRead-only	0x00000000	TLB entry data addressed by TBU debug read pointer.
SMMU_DBGRPTRTCU	0x0000000088	32	rwNormal read/write	0x00000000	Address of an entry from a specific cache in TCU.
SMMU_DBGRDATATCU	0x000000008C	32	roRead-only	0x00000000	Cache entry data addressed by TCU debug read pointer.
SMMU_STLBIVALM_low	0x00000000A0	32	woWrite-only	0x00000000	Invalidates all unlocked entries associated with MONC banks, that match the specified virtual address.
SMMU_STLBIVALM_high	0x00000000A4	32	woWrite-only	0x00000000	Invalidates all unlocked entries associated with MONC banks, that match the specified virtual address.
SMMU_STLBIVAM_low	0x00000000A8	32	woWrite-only	0x00000000	Invalidates all unlocked entries associated with MONC banks, that match the specified virtual address.
SMMU_STLBIVAM_high	0x00000000AC	32	woWrite-only	0x00000000	Invalidates all unlocked entries associated with MONC banks, that match the specified virtual address.
SMMU_STLBIALLM	0x00000000BC	32	woWrite-only	0x00000000	Invalidates all unlocked entries associated with MONC banks in the TLB.
SMMU_NSCR0	0x0000000400	32	mixedMixed types. See bit-field details.	0x00200001	Provides top-level control of the SMMU.
SMMU_NSACR	0x0000000410	32	rwNormal read/write	0x0400001C	Provides IMPLEMENTATION DEFINED functionality.
SMMU_NSGFAR_low	0x0000000440	32	rwNormal read/write	0x00000000	Contains the input address of an erroneous request reported by SMMU_GFSR.
SMMU_NSGFAR_high	0x0000000444	32	rwNormal read/write	0x00000000	Contains the input address of an erroneous request reported by SMMU_GFSR.
SMMU_NSGFSR	0x0000000448	32	woWrite-only	0x00000000	Gives the fault status for each of the following possible faults.
SMMU_NSGFSRRESTORE	0x000000044C	32	woWrite-only	0x00000000	Restores the state of SMMU_GFSR, after a reset, for example.
SMMU_NSGFSYNR0	0x0000000450	32	mixedMixed types. See bit-field details.	0x00000000	Contains fault syndrome information relating to SMMU_GFSR.
SMMU_NSGFSYNDR1	0x0000000454	32	mixedMixed types. See bit-field details.	0x00000000	Contains fault syndrome information relating to SMMU_GFSR.
SMMU_NSTLBGSYNC	0x0000000470	32	woWrite-only	0x00000000	Starts a global synchronization operation that ensures the completion of any previously accepted TLB Invalidate operation. As a minimum, the operation applies to the specified security state, and includes all TLB Invalidate operations initiated in context banks associated with that security state.
SMMU_NSTLBGSTATUS	0x0000000474	32	roRead-only	0x00000000	Gives the status of a TLB maintenance operation.
SMMU_SMR0	0x0000000800	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR1	0x0000000804	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR2	0x0000000808	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR3	0x000000080C	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR4	0x0000000810	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR5	0x0000000814	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR6	0x0000000818	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR7	0x000000081C	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR8	0x0000000820	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR9	0x0000000824	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR10	0x0000000828	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR11	0x000000082C	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR12	0x0000000830	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR13	0x0000000834	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR14	0x0000000838	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR15	0x000000083C	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR16	0x0000000840	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR17	0x0000000844	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR18	0x0000000848	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR19	0x000000084C	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR20	0x0000000850	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR21	0x0000000854	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR22	0x0000000858	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR23	0x000000085C	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR24	0x0000000860	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR25	0x0000000864	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR26	0x0000000868	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR27	0x000000086C	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR28	0x0000000870	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR29	0x0000000874	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR30	0x0000000878	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR31	0x000000087C	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR32	0x0000000880	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR33	0x0000000884	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR34	0x0000000888	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR35	0x000000088C	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR36	0x0000000890	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR37	0x0000000894	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR38	0x0000000898	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR39	0x000000089C	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR40	0x00000008A0	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR41	0x00000008A4	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR42	0x00000008A8	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR43	0x00000008AC	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR44	0x00000008B0	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR45	0x00000008B4	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR46	0x00000008B8	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_SMR47	0x00000008BC	32	rwNormal read/write	0x00000000	Matches a transaction with a particular Stream mapping register group.
SMMU_S2CR0	0x0000000C00	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR1	0x0000000C04	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR2	0x0000000C08	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR3	0x0000000C0C	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR4	0x0000000C10	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR5	0x0000000C14	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR6	0x0000000C18	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR7	0x0000000C1C	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR8	0x0000000C20	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR9	0x0000000C24	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR10	0x0000000C28	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR11	0x0000000C2C	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR12	0x0000000C30	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR13	0x0000000C34	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR14	0x0000000C38	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR15	0x0000000C3C	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR16	0x0000000C40	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR17	0x0000000C44	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR18	0x0000000C48	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR19	0x0000000C4C	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR20	0x0000000C50	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR21	0x0000000C54	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR22	0x0000000C58	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR23	0x0000000C5C	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR24	0x0000000C60	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR25	0x0000000C64	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR26	0x0000000C68	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR27	0x0000000C6C	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR28	0x0000000C70	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR29	0x0000000C74	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR30	0x0000000C78	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR31	0x0000000C7C	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR32	0x0000000C80	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR33	0x0000000C84	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR34	0x0000000C88	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR35	0x0000000C8C	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR36	0x0000000C90	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR37	0x0000000C94	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR38	0x0000000C98	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR39	0x0000000C9C	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR40	0x0000000CA0	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR41	0x0000000CA4	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR42	0x0000000CA8	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR43	0x0000000CAC	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR44	0x0000000CB0	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR45	0x0000000CB4	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR46	0x0000000CB8	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_S2CR47	0x0000000CBC	32	rwNormal read/write	0x00020000	Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.
SMMU_PIDR4	0x0000000FD0	32	roRead-only	0x00000004	Peripheral Identificaation register 4
SMMU_PIDR5	0x0000000FD4	32	roRead-only	0x00000000	Peripheral Identificaation register 5
SMMU_PIDR6	0x0000000FD8	32	roRead-only	0x00000000	Peripheral Identificaation register 6
SMMU_PIDR7	0x0000000FDC	32	roRead-only	0x00000000	Peripheral Identificaation register 7
SMMU_PIDR0	0x0000000FE0	32	roRead-only	0x00000081	Peripheral Identificaation register 0
SMMU_PIDR1	0x0000000FE4	32	roRead-only	0x000000B4	Peripheral Identificaation register 1
SMMU_PIDR2	0x0000000FE8	32	roRead-only	0x0000001B	Peripheral Identificaation register 2
SMMU_PIDR3	0x0000000FEC	32	roRead-only	0x00000000	Peripheral Identificaation register 3
SMMU_CIDR0	0x0000000FF0	32	roRead-only	0x0000000D	Component Identification register 0
SMMU_CIDR1	0x0000000FF4	32	roRead-only	0x000000F0	Component Identification register 1
SMMU_CIDR2	0x0000000FF8	32	roRead-only	0x00000005	Component Identification register 2
SMMU_CIDR3	0x0000000FFC	32	roRead-only	0x000000B1	Component Identification register 3
SMMU_CBAR0	0x0000001000	32	mixedMixed types. See bit-field details.	0x00020000	Specifies configuration attributes for translation context bank.
SMMU_CBAR1	0x0000001004	32	mixedMixed types. See bit-field details.	0x00020000	Specifies configuration attributes for translation context bank.
SMMU_CBAR2	0x0000001008	32	mixedMixed types. See bit-field details.	0x00020000	Specifies configuration attributes for translation context bank.
SMMU_CBAR3	0x000000100C	32	mixedMixed types. See bit-field details.	0x00020000	Specifies configuration attributes for translation context bank.
SMMU_CBAR4	0x0000001010	32	mixedMixed types. See bit-field details.	0x00020000	Specifies configuration attributes for translation context bank.
SMMU_CBAR5	0x0000001014	32	mixedMixed types. See bit-field details.	0x00020000	Specifies configuration attributes for translation context bank.
SMMU_CBAR6	0x0000001018	32	mixedMixed types. See bit-field details.	0x00020000	Specifies configuration attributes for translation context bank.
SMMU_CBAR7	0x000000101C	32	mixedMixed types. See bit-field details.	0x00020000	Specifies configuration attributes for translation context bank.
SMMU_CBAR8	0x0000001020	32	mixedMixed types. See bit-field details.	0x00020000	Specifies configuration attributes for translation context bank.
SMMU_CBAR9	0x0000001024	32	mixedMixed types. See bit-field details.	0x00020000	Specifies configuration attributes for translation context bank.
SMMU_CBAR10	0x0000001028	32	mixedMixed types. See bit-field details.	0x00020000	Specifies configuration attributes for translation context bank.
SMMU_CBAR11	0x000000102C	32	mixedMixed types. See bit-field details.	0x00020000	Specifies configuration attributes for translation context bank.
SMMU_CBAR12	0x0000001030	32	mixedMixed types. See bit-field details.	0x00020000	Specifies configuration attributes for translation context bank.
SMMU_CBAR13	0x0000001034	32	mixedMixed types. See bit-field details.	0x00020000	Specifies configuration attributes for translation context bank.
SMMU_CBAR14	0x0000001038	32	mixedMixed types. See bit-field details.	0x00020000	Specifies configuration attributes for translation context bank.
SMMU_CBAR15	0x000000103C	32	mixedMixed types. See bit-field details.	0x00020000	Specifies configuration attributes for translation context bank.
SMMU_CBFRSYNRA0	0x0000001400	32	mixedMixed types. See bit-field details.	0x00000000	Gives fault syndrome information about the access that caused an exception in the associated translation context bank.
SMMU_CBFRSYNRA1	0x0000001404	32	mixedMixed types. See bit-field details.	0x00000000	Gives fault syndrome information about the access that caused an exception in the associated translation context bank.
SMMU_CBFRSYNRA2	0x0000001408	32	mixedMixed types. See bit-field details.	0x00000000	Gives fault syndrome information about the access that caused an exception in the associated translation context bank.
SMMU_CBFRSYNRA3	0x000000140C	32	mixedMixed types. See bit-field details.	0x00000000	Gives fault syndrome information about the access that caused an exception in the associated translation context bank.
SMMU_CBFRSYNRA4	0x0000001410	32	mixedMixed types. See bit-field details.	0x00000000	Gives fault syndrome information about the access that caused an exception in the associated translation context bank.
SMMU_CBFRSYNRA5	0x0000001414	32	mixedMixed types. See bit-field details.	0x00000000	Gives fault syndrome information about the access that caused an exception in the associated translation context bank.
SMMU_CBFRSYNRA6	0x0000001418	32	mixedMixed types. See bit-field details.	0x00000000	Gives fault syndrome information about the access that caused an exception in the associated translation context bank.
SMMU_CBFRSYNRA7	0x000000141C	32	mixedMixed types. See bit-field details.	0x00000000	Gives fault syndrome information about the access that caused an exception in the associated translation context bank.
SMMU_CBFRSYNRA8	0x0000001420	32	mixedMixed types. See bit-field details.	0x00000000	Gives fault syndrome information about the access that caused an exception in the associated translation context bank.
SMMU_CBFRSYNRA9	0x0000001424	32	mixedMixed types. See bit-field details.	0x00000000	Gives fault syndrome information about the access that caused an exception in the associated translation context bank.
SMMU_CBFRSYNRA10	0x0000001428	32	mixedMixed types. See bit-field details.	0x00000000	Gives fault syndrome information about the access that caused an exception in the associated translation context bank.
SMMU_CBFRSYNRA11	0x000000142C	32	mixedMixed types. See bit-field details.	0x00000000	Gives fault syndrome information about the access that caused an exception in the associated translation context bank.
SMMU_CBFRSYNRA12	0x0000001430	32	mixedMixed types. See bit-field details.	0x00000000	Gives fault syndrome information about the access that caused an exception in the associated translation context bank.
SMMU_CBFRSYNRA13	0x0000001434	32	mixedMixed types. See bit-field details.	0x00000000	Gives fault syndrome information about the access that caused an exception in the associated translation context bank.
SMMU_CBFRSYNRA14	0x0000001438	32	mixedMixed types. See bit-field details.	0x00000000	Gives fault syndrome information about the access that caused an exception in the associated translation context bank.
SMMU_CBFRSYNRA15	0x000000143C	32	mixedMixed types. See bit-field details.	0x00000000	Gives fault syndrome information about the access that caused an exception in the associated translation context bank.
SMMU_CBA2R0	0x0000001800	32	rwNormal read/write	0x00000000	Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies.
SMMU_CBA2R1	0x0000001804	32	rwNormal read/write	0x00000000	Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies.
SMMU_CBA2R2	0x0000001808	32	rwNormal read/write	0x00000000	Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies.
SMMU_CBA2R3	0x000000180C	32	rwNormal read/write	0x00000000	Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies.
SMMU_CBA2R4	0x0000001810	32	rwNormal read/write	0x00000000	Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies.
SMMU_CBA2R5	0x0000001814	32	rwNormal read/write	0x00000000	Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies.
SMMU_CBA2R6	0x0000001818	32	rwNormal read/write	0x00000000	Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies.
SMMU_CBA2R7	0x000000181C	32	rwNormal read/write	0x00000000	Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies.
SMMU_CBA2R8	0x0000001820	32	rwNormal read/write	0x00000000	Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies.
SMMU_CBA2R9	0x0000001824	32	rwNormal read/write	0x00000000	Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies.
SMMU_CBA2R10	0x0000001828	32	rwNormal read/write	0x00000000	Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies.
SMMU_CBA2R11	0x000000182C	32	rwNormal read/write	0x00000000	Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies.
SMMU_CBA2R12	0x0000001830	32	rwNormal read/write	0x00000000	Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies.
SMMU_CBA2R13	0x0000001834	32	rwNormal read/write	0x00000000	Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies.
SMMU_CBA2R14	0x0000001838	32	rwNormal read/write	0x00000000	Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies.
SMMU_CBA2R15	0x000000183C	32	rwNormal read/write	0x00000000	Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies.
SMMU_ITCTRL	0x0000002000	32	rwNormal read/write	0x00000000	This register enables the component to switch from functional mode to integration mode. You can directly control the inputs and outputs in integration mode.
SMMU_ITIP	0x0000002004	32	roRead-only	0x00000000	Enables the MMU-500 to read the status of the spniden signal.
SMMU_ITOP_GLBL	0x0000002008	32	mixedMixed types. See bit-field details.	0x00000000	For integration test purposes, allows to enable or disable secure and nonsecure interrupts and write or read most significant bits of TCU MTLB and IPA RAMS.
SMMU_ITOP_PERF_INDEX	0x000000200C	32	woWrite-only	0x00000000	Enables TBU performance interrupts.
SMMU_ITOP_CXT0TO31_RAM0	0x0000002010	32	woWrite-only	0x00000000	Enable the context performance interrupts.
SMMU_TBUQOS0	0x0000002100	32	rwNormal read/write	0x00000000	Specify the QoS for TBUs,when the TBUn is in the range of 0-7.
SMMU_PER	0x0000002200	32	roRead-only	0x00000000	Checks for parity errors in TCU and TBU RAMs.
SMMU_TBU_PWR_STATUS	0x0000002204	32	roRead-only	0x00000000	Provides the power status of TBUs.
PMEVCNTR0	0x0000003000	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
PMEVCNTR1	0x0000003004	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
PMEVCNTR2	0x0000003008	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
PMEVCNTR3	0x000000300C	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
PMEVCNTR4	0x0000003010	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
PMEVCNTR5	0x0000003014	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
PMEVCNTR6	0x0000003018	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
PMEVCNTR7	0x000000301C	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
PMEVCNTR8	0x0000003020	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
PMEVCNTR9	0x0000003024	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
PMEVCNTR10	0x0000003028	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
PMEVCNTR11	0x000000302C	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
PMEVCNTR12	0x0000003030	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
PMEVCNTR13	0x0000003034	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
PMEVCNTR14	0x0000003038	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
PMEVCNTR15	0x000000303C	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
PMEVCNTR16	0x0000003040	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
PMEVCNTR17	0x0000003044	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
PMEVCNTR18	0x0000003048	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
PMEVCNTR19	0x000000304C	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
PMEVCNTR20	0x0000003050	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
PMEVCNTR21	0x0000003054	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
PMEVCNTR22	0x0000003058	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
PMEVCNTR23	0x000000305C	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
PMEVTYPER0	0x0000003400	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
PMEVTYPER1	0x0000003404	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
PMEVTYPER2	0x0000003408	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
PMEVTYPER3	0x000000340C	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
PMEVTYPER4	0x0000003410	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
PMEVTYPER5	0x0000003414	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
PMEVTYPER6	0x0000003418	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
PMEVTYPER7	0x000000341C	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
PMEVTYPER8	0x0000003420	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
PMEVTYPER9	0x0000003424	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
PMEVTYPER10	0x0000003428	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
PMEVTYPER11	0x000000342C	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
PMEVTYPER12	0x0000003430	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
PMEVTYPER13	0x0000003434	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
PMEVTYPER14	0x0000003438	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
PMEVTYPER15	0x000000343C	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
PMEVTYPER16	0x0000003440	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
PMEVTYPER17	0x0000003444	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
PMEVTYPER18	0x0000003448	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
PMEVTYPER19	0x000000344C	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
PMEVTYPER20	0x0000003450	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
PMEVTYPER21	0x0000003454	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
PMEVTYPER22	0x0000003458	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
PMEVTYPER23	0x000000345C	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
PMCGCR0	0x0000003800	32	mixedMixed types. See bit-field details.	0x04000000	Controls Counter group behavior.
PMCGCR1	0x0000003804	32	mixedMixed types. See bit-field details.	0x04010000	Controls Counter group behavior.
PMCGCR2	0x0000003808	32	mixedMixed types. See bit-field details.	0x04020000	Controls Counter group behavior.
PMCGCR3	0x000000380C	32	mixedMixed types. See bit-field details.	0x04030000	Controls Counter group behavior.
PMCGCR4	0x0000003810	32	mixedMixed types. See bit-field details.	0x04040000	Controls Counter group behavior.
PMCGCR5	0x0000003814	32	mixedMixed types. See bit-field details.	0x04050000	Controls Counter group behavior.
PMCGSMR0	0x0000003A00	32	rwNormal read/write	0x00000000	Specifies StreamID filtering of the events counted in a Counter group
PMCGSMR1	0x0000003A04	32	rwNormal read/write	0x00000000	Specifies StreamID filtering of the events counted in a Counter group
PMCGSMR2	0x0000003A08	32	rwNormal read/write	0x00000000	Specifies StreamID filtering of the events counted in a Counter group
PMCGSMR3	0x0000003A0C	32	rwNormal read/write	0x00000000	Specifies StreamID filtering of the events counted in a Counter group
PMCGSMR4	0x0000003A10	32	rwNormal read/write	0x00000000	Specifies StreamID filtering of the events counted in a Counter group
PMCGSMR5	0x0000003A14	32	rwNormal read/write	0x00000000	Specifies StreamID filtering of the events counted in a Counter group
PMCNTENSET	0x0000003C00	32	woWrite-only	0x00000000	Performance Monitor Counter Enable Set registers are used to enable the event counters PMEVCNTRxx.
PMCNTENCLR	0x0000003C20	32	woWrite-only	0x00000000	Performance Monitor Counter Enable Clear registers are used to disable the event counters PMEVCNTRxx.
PMINTENSET	0x0000003C40	32	woWrite-only	0x00000000	Performance Monitor Interrupt Enable Set registers are used enable the generation of interrupts on overflows of the event counters.
PMINTENCLR	0x0000003C60	32	woWrite-only	0x00000000	Performance Monitor Interrupt Enable Clear registers are used disable the generation of interrupts on overflows of the event counters.
PMOVSCLR	0x0000003C80	32	woWrite-only	0x00000000	Performance Monitor Overflow Status Clear registers are used to clear the overflow status of the event registers.
PMOVSSET	0x0000003CC0	32	woWrite-only	0x00000000	Performance Monitor Overflow Status Set registers contain overflow status for the event counters.
PMCFGR	0x0000003E00	32	roRead-only	0x05011F17	Performance Monitor Configuration register containss PMU specific configuration data.
PMCR	0x0000003E04	32	mixedMixed types. See bit-field details.	0x00000000	Performance Monitor Configuration register controls the behaviour of the event counters.
PMCEID0	0x0000003E20	32	roRead-only	0x00030303	Performance Monitor Common Event Identification register 0 describes the event classes supported by the SMMU implementation.
PMAUTHSTATUS	0x0000003FB8	32	roRead-only	0x00000080	Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug permissions.
PMDEVTYPE	0x0000003FCC	32	roRead-only	0x00000056	Performance Monitor Device Type register provides the Coresight device type information for the PerformanceMonitors.
SMMU_CB0_SCTLR	0x0000010000	32	mixedMixed types. See bit-field details.	0x00000100	The System Control register provides the top level control of the translation system for the related Context bank.
SMMU_CB0_ACTLR	0x0000010004	32	rwNormal read/write	0x00000003	The Auxillary Control register provides implementation specific configuration and control options.
SMMU_CB0_RESUME	0x0000010008	32	woWrite-only	0x00000000	The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition.
SMMU_CB0_TCR2	0x0000010010	32	mixedMixed types. See bit-field details.	0x00000060	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB0_TTBR0_low	0x0000010020	32	mixedMixed types. See bit-field details.	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB0_TTBR0_high	0x0000010024	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB0_TTBR1_low	0x0000010028	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB0_TTBR1_high	0x000001002C	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB0_TCR_lpae	0x0000010030	32	rwNormal read/write	0x00000000	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB0_CONTEXTIDR	0x0000010034	32	rwNormal read/write	0x00000000	Identifies the current process identifier and the current address space identifier
SMMU_CB0_PRRR_MAIR0	0x0000010038	32	rwNormal read/write	0x00000000	Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX, C, and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB0_NMRR_MAIR1	0x000001003C	32	rwNormal read/write	0x00000000	Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB0_FSR	0x0000010058	32	woWrite-only	0x00000000	Provides memory system fault status information.
SMMU_CB0_FSRRESTORE	0x000001005C	32	woWrite-only	0x00000000	Restores the state of SMMU_CBn_FSR, after a reset, for example.
SMMU_CB0_FAR_low	0x0000010060	32	rwNormal read/write	0x00000000	Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception.
SMMU_CB0_FAR_high	0x0000010064	32	rwNormal read/write	0x00000000	Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception.
SMMU_CB0_FSYNR0	0x0000010068	32	mixedMixed types. See bit-field details.	0x00000000	Holds fault syndrome information about the memory access that caused a synchronous abort exception
SMMU_CB0_IPAFAR_low	0x0000010070	32	mixedMixed types. See bit-field details.	0x00000000	The stage 1 IPA Fault Address Lower bits [31:0] Register.
SMMU_CB0_IPAFAR_high	0x0000010074	32	rwNormal read/write	0x00000000	The stage 1 IPA Fault Address Upper bits [63:32] Register
SMMU_CB0_TLBIVA_low	0x0000010600	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate.
SMMU_CB0_TLBIVA_high	0x0000010604	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate
SMMU_CB0_TLBIVAA_low	0x0000010608	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB0_TLBIVAA_high	0x000001060C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB0_TLBIASID	0x0000010610	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the ASID provided as an argument
SMMU_CB0_TLBIALL	0x0000010618	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor, for HYPC banks, ii)Non-secure, using the VMID of the context bank, for Non-secure, non-HYPC context banks,iii) Secure, using any ASID, for Secure context banks.
SMMU_CB0_TLBIVAL_low	0x0000010620	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB0_TLBIVAL_high	0x0000010624	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB0_TLBIVAAL_low	0x0000010628	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB0_TLBIVAAL_high	0x000001062C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB0_TLBIIPAS2_low	0x0000010630	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB0_TLBIIPAS2_high	0x0000010634	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB0_TLBIIPAS2L_low	0x0000010638	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB0_TLBIIPAS2L_high	0x000001063C	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB0_TLBSYNC	0x00000107F0	32	woWrite-only	0x00000000	Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank.
SMMU_CB0_TLBSTATUS	0x00000107F4	32	roRead-only	0x00000000	Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation
SMMU_CB0_PMEVCNTR0	0x0000010E00	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB0_PMEVCNTR1	0x0000010E04	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB0_PMEVCNTR2	0x0000010E08	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB0_PMEVCNTR3	0x0000010E0C	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB0_PMEVTYPER0	0x0000010E80	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB0_PMEVTYPER1	0x0000010E84	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB0_PMEVTYPER2	0x0000010E88	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB0_PMEVTYPER3	0x0000010E8C	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB0_PMCFGR	0x0000010F00	32	roRead-only	0x00011F03	Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data.
SMMU_CB0_PMCR	0x0000010F04	32	mixedMixed types. See bit-field details.	0x00000000	Provides the equivalent of the PMCR register, in the register map of a translation context bank. PMCR provides controls for the Performance Monitors.
SMMU_CB0_PMCEID	0x0000010F20	32	roRead-only	0x00030303	Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register, in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation.
SMMU_CB0_PMCNTENSE	0x0000010F40	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENSETx register, in the register map of a translation context bank. Enables any implemented event counters.
SMMU_CB0_PMCNTENCLR	0x0000010F44	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENCLRx register, in the register map of a translation context bank. Disables any implemented event counter.
SMMU_CB0_PMCNTENSET	0x0000010F48	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter
SMMU_CB0_PMINTENCLR	0x0000010F4C	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter.
SMMU_CB0_PMOVSCLR	0x0000010F50	32	woWrite-only	0x00000000	Provides the equivalent of the PMOVSCLRx register, in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter.
SMMU_CB0_PMOVSSET	0x0000010F58	32	woWrite-only	0x00000000	Provides the equivalent of PMOVSSETx, in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters.
smmu_cb0_pmauthstatus	0x0000010FB8	32	roRead-only	0x00000080	Provides the equivalent of the PMAUTHSTATUS register, in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug permissions
SMMU_CB1_SCTLR	0x0000011000	32	mixedMixed types. See bit-field details.	0x00000100	The System Control register provides the top level control of the translation system for the related Context bank.
SMMU_CB1_ACTLR	0x0000011004	32	rwNormal read/write	0x00000003	The Auxillary Control register provides implementation specific configuration and control options.
SMMU_CB1_RESUME	0x0000011008	32	woWrite-only	0x00000000	The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition.
SMMU_CB1_TCR2	0x0000011010	32	mixedMixed types. See bit-field details.	0x00000060	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB1_TTBR0_low	0x0000011020	32	mixedMixed types. See bit-field details.	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB1_TTBR0_high	0x0000011024	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB1_TTBR1_low	0x0000011028	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB1_TTBR1_high	0x000001102C	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB1_TCR_lpae	0x0000011030	32	rwNormal read/write	0x00000000	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB1_CONTEXTIDR	0x0000011034	32	rwNormal read/write	0x00000000	Identifies the current process identifier and the current address space identifier
SMMU_CB1_PRRR_MAIR0	0x0000011038	32	rwNormal read/write	0x00000000	Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX, C, and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB1_NMRR_MAIR1	0x000001103C	32	rwNormal read/write	0x00000000	Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB1_FSR	0x0000011058	32	woWrite-only	0x00000000	Provides memory system fault status information.
SMMU_CB1_FSRRESTORE	0x000001105C	32	woWrite-only	0x00000000	Restores the state of SMMU_CBn_FSR, after a reset, for example.
SMMU_CB1_FAR_low	0x0000011060	32	rwNormal read/write	0x00000000	Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception.
SMMU_CB1_FAR_high	0x0000011064	32	rwNormal read/write	0x00000000	Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception.
SMMU_CB1_FSYNR0	0x0000011068	32	mixedMixed types. See bit-field details.	0x00000000	Holds fault syndrome information about the memory access that caused a synchronous abort exception
SMMU_CB1_IPAFAR_low	0x0000011070	32	mixedMixed types. See bit-field details.	0x00000000	The stage 1 IPA Fault Address Lower bits [31:0] Register.
SMMU_CB1_IPAFAR_high	0x0000011074	32	rwNormal read/write	0x00000000	The stage 1 IPA Fault Address Upper bits [63:32] Register
SMMU_CB1_TLBIVA_low	0x0000011600	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate.
SMMU_CB1_TLBIVA_high	0x0000011604	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate
SMMU_CB1_TLBIVAA_low	0x0000011608	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB1_TLBIVAA_high	0x000001160C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB1_TLBIASID	0x0000011610	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the ASID provided as an argument
SMMU_CB1_TLBIALL	0x0000011618	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor, for HYPC banks, ii)Non-secure, using the VMID of the context bank, for Non-secure, non-HYPC context banks,iii) Secure, using any ASID, for Secure context banks.
SMMU_CB1_TLBIVAL_low	0x0000011620	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB1_TLBIVAL_high	0x0000011624	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB1_TLBIVAAL_low	0x0000011628	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB1_TLBIVAAL_high	0x000001162C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB1_TLBIIPAS2_low	0x0000011630	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB1_TLBIIPAS2_high	0x0000011634	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB1_TLBIIPAS2L_low	0x0000011638	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB1_TLBIIPAS2L_high	0x000001163C	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB1_TLBSYNC	0x00000117F0	32	woWrite-only	0x00000000	Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank.
SMMU_CB1_TLBSTATUS	0x00000117F4	32	roRead-only	0x00000000	Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation
SMMU_CB1_PMEVCNTR0	0x0000011E00	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB1_PMEVCNTR1	0x0000011E04	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB1_PMEVCNTR2	0x0000011E08	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB1_PMEVCNTR3	0x0000011E0C	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB1_PMEVTYPER0	0x0000011E80	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB1_PMEVTYPER1	0x0000011E84	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB1_PMEVTYPER2	0x0000011E88	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB1_PMEVTYPER3	0x0000011E8C	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB1_PMCFGR	0x0000011F00	32	roRead-only	0x00011F03	Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data.
SMMU_CB1_PMCR	0x0000011F04	32	mixedMixed types. See bit-field details.	0x00000000	Provides the equivalent of the PMCR register, in the register map of a translation context bank. PMCR provides controls for the Performance Monitors.
SMMU_CB1_PMCEID	0x0000011F20	32	roRead-only	0x00030303	Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register, in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation.
SMMU_CB1_PMCNTENSE	0x0000011F40	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENSETx register, in the register map of a translation context bank. Enables any implemented event counters.
SMMU_CB1_PMCNTENCLR	0x0000011F44	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENCLRx register, in the register map of a translation context bank. Disables any implemented event counter.
SMMU_CB1_PMCNTENSET	0x0000011F48	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter
SMMU_CB1_PMINTENCLR	0x0000011F4C	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter.
SMMU_CB1_PMOVSCLR	0x0000011F50	32	woWrite-only	0x00000000	Provides the equivalent of the PMOVSCLRx register, in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter.
SMMU_CB1_PMOVSSET	0x0000011F58	32	woWrite-only	0x00000000	Provides the equivalent of PMOVSSETx, in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters.
smmu_cb1_pmauthstatus	0x0000011FB8	32	roRead-only	0x00000080	Provides the equivalent of the PMAUTHSTATUS register, in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug permissions
SMMU_CB2_SCTLR	0x0000012000	32	mixedMixed types. See bit-field details.	0x00000100	The System Control register provides the top level control of the translation system for the related Context bank.
SMMU_CB2_ACTLR	0x0000012004	32	rwNormal read/write	0x00000003	The Auxillary Control register provides implementation specific configuration and control options.
SMMU_CB2_RESUME	0x0000012008	32	woWrite-only	0x00000000	The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition.
SMMU_CB2_TCR2	0x0000012010	32	mixedMixed types. See bit-field details.	0x00000060	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB2_TTBR0_low	0x0000012020	32	mixedMixed types. See bit-field details.	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB2_TTBR0_high	0x0000012024	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB2_TTBR1_low	0x0000012028	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB2_TTBR1_high	0x000001202C	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB2_TCR_lpae	0x0000012030	32	rwNormal read/write	0x00000000	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB2_CONTEXTIDR	0x0000012034	32	rwNormal read/write	0x00000000	Identifies the current process identifier and the current address space identifier
SMMU_CB2_PRRR_MAIR0	0x0000012038	32	rwNormal read/write	0x00000000	Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX, C, and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB2_NMRR_MAIR1	0x000001203C	32	rwNormal read/write	0x00000000	Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB2_FSR	0x0000012058	32	woWrite-only	0x00000000	Provides memory system fault status information.
SMMU_CB2_FSRRESTORE	0x000001205C	32	woWrite-only	0x00000000	Restores the state of SMMU_CBn_FSR, after a reset, for example.
SMMU_CB2_FAR_low	0x0000012060	32	rwNormal read/write	0x00000000	Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception.
SMMU_CB2_FAR_high	0x0000012064	32	rwNormal read/write	0x00000000	Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception.
SMMU_CB2_FSYNR0	0x0000012068	32	mixedMixed types. See bit-field details.	0x00000000	Holds fault syndrome information about the memory access that caused a synchronous abort exception
SMMU_CB2_IPAFAR_low	0x0000012070	32	mixedMixed types. See bit-field details.	0x00000000	The stage 1 IPA Fault Address Lower bits [31:0] Register.
SMMU_CB2_IPAFAR_high	0x0000012074	32	rwNormal read/write	0x00000000	The stage 1 IPA Fault Address Upper bits [63:32] Register
SMMU_CB2_TLBIVA_low	0x0000012600	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate.
SMMU_CB2_TLBIVA_high	0x0000012604	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate
SMMU_CB2_TLBIVAA_low	0x0000012608	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB2_TLBIVAA_high	0x000001260C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB2_TLBIASID	0x0000012610	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the ASID provided as an argument
SMMU_CB2_TLBIALL	0x0000012618	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor, for HYPC banks, ii)Non-secure, using the VMID of the context bank, for Non-secure, non-HYPC context banks,iii) Secure, using any ASID, for Secure context banks.
SMMU_CB2_TLBIVAL_low	0x0000012620	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB2_TLBIVAL_high	0x0000012624	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB2_TLBIVAAL_low	0x0000012628	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB2_TLBIVAAL_high	0x000001262C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB2_TLBIIPAS2_low	0x0000012630	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB2_TLBIIPAS2_high	0x0000012634	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB2_TLBIIPAS2L_low	0x0000012638	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB2_TLBIIPAS2L_high	0x000001263C	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB2_TLBSYNC	0x00000127F0	32	woWrite-only	0x00000000	Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank.
SMMU_CB2_TLBSTATUS	0x00000127F4	32	roRead-only	0x00000000	Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation
SMMU_CB2_PMEVCNTR0	0x0000012E00	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB2_PMEVCNTR1	0x0000012E04	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB2_PMEVCNTR2	0x0000012E08	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB2_PMEVCNTR3	0x0000012E0C	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB2_PMEVTYPER0	0x0000012E80	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB2_PMEVTYPER1	0x0000012E84	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB2_PMEVTYPER2	0x0000012E88	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB2_PMEVTYPER3	0x0000012E8C	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB2_PMCFGR	0x0000012F00	32	roRead-only	0x00011F03	Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data.
SMMU_CB2_PMCR	0x0000012F04	32	mixedMixed types. See bit-field details.	0x00000000	Provides the equivalent of the PMCR register, in the register map of a translation context bank. PMCR provides controls for the Performance Monitors.
SMMU_CB2_PMCEID	0x0000012F20	32	roRead-only	0x00030303	Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register, in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation.
SMMU_CB2_PMCNTENSE	0x0000012F40	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENSETx register, in the register map of a translation context bank. Enables any implemented event counters.
SMMU_CB2_PMCNTENCLR	0x0000012F44	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENCLRx register, in the register map of a translation context bank. Disables any implemented event counter.
SMMU_CB2_PMCNTENSET	0x0000012F48	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter
SMMU_CB2_PMINTENCLR	0x0000012F4C	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter.
SMMU_CB2_PMOVSCLR	0x0000012F50	32	woWrite-only	0x00000000	Provides the equivalent of the PMOVSCLRx register, in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter.
SMMU_CB2_PMOVSSET	0x0000012F58	32	woWrite-only	0x00000000	Provides the equivalent of PMOVSSETx, in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters.
smmu_cb2_pmauthstatus	0x0000012FB8	32	roRead-only	0x00000080	Provides the equivalent of the PMAUTHSTATUS register, in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug permissions
SMMU_CB3_SCTLR	0x0000013000	32	mixedMixed types. See bit-field details.	0x00000100	The System Control register provides the top level control of the translation system for the related Context bank.
SMMU_CB3_ACTLR	0x0000013004	32	rwNormal read/write	0x00000003	The Auxillary Control register provides implementation specific configuration and control options.
SMMU_CB3_RESUME	0x0000013008	32	woWrite-only	0x00000000	The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition.
SMMU_CB3_TCR2	0x0000013010	32	mixedMixed types. See bit-field details.	0x00000060	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB3_TTBR0_low	0x0000013020	32	mixedMixed types. See bit-field details.	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB3_TTBR0_high	0x0000013024	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB3_TTBR1_low	0x0000013028	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB3_TTBR1_high	0x000001302C	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB3_TCR_lpae	0x0000013030	32	rwNormal read/write	0x00000000	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB3_CONTEXTIDR	0x0000013034	32	rwNormal read/write	0x00000000	Identifies the current process identifier and the current address space identifier
SMMU_CB3_PRRR_MAIR0	0x0000013038	32	rwNormal read/write	0x00000000	Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX, C, and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB3_NMRR_MAIR1	0x000001303C	32	rwNormal read/write	0x00000000	Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB3_FSR	0x0000013058	32	woWrite-only	0x00000000	Provides memory system fault status information.
SMMU_CB3_FSRRESTORE	0x000001305C	32	woWrite-only	0x00000000	Restores the state of SMMU_CBn_FSR, after a reset, for example.
SMMU_CB3_FAR_low	0x0000013060	32	rwNormal read/write	0x00000000	Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception.
SMMU_CB3_FAR_high	0x0000013064	32	rwNormal read/write	0x00000000	Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception.
SMMU_CB3_FSYNR0	0x0000013068	32	mixedMixed types. See bit-field details.	0x00000000	Holds fault syndrome information about the memory access that caused a synchronous abort exception
SMMU_CB3_IPAFAR_low	0x0000013070	32	mixedMixed types. See bit-field details.	0x00000000	The stage 1 IPA Fault Address Lower bits [31:0] Register.
SMMU_CB3_IPAFAR_high	0x0000013074	32	rwNormal read/write	0x00000000	The stage 1 IPA Fault Address Upper bits [63:32] Register
SMMU_CB3_TLBIVA_low	0x0000013600	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate.
SMMU_CB3_TLBIVA_high	0x0000013604	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate
SMMU_CB3_TLBIVAA_low	0x0000013608	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB3_TLBIVAA_high	0x000001360C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB3_TLBIASID	0x0000013610	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the ASID provided as an argument
SMMU_CB3_TLBIALL	0x0000013618	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor, for HYPC banks, ii)Non-secure, using the VMID of the context bank, for Non-secure, non-HYPC context banks,iii) Secure, using any ASID, for Secure context banks.
SMMU_CB3_TLBIVAL_low	0x0000013620	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB3_TLBIVAL_high	0x0000013624	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB3_TLBIVAAL_low	0x0000013628	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB3_TLBIVAAL_high	0x000001362C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB3_TLBIIPAS2_low	0x0000013630	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB3_TLBIIPAS2_high	0x0000013634	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB3_TLBIIPAS2L_low	0x0000013638	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB3_TLBIIPAS2L_high	0x000001363C	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB3_TLBSYNC	0x00000137F0	32	woWrite-only	0x00000000	Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank.
SMMU_CB3_TLBSTATUS	0x00000137F4	32	roRead-only	0x00000000	Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation
SMMU_CB3_PMEVCNTR0	0x0000013E00	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB3_PMEVCNTR1	0x0000013E04	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB3_PMEVCNTR2	0x0000013E08	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB3_PMEVCNTR3	0x0000013E0C	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB3_PMEVTYPER0	0x0000013E80	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB3_PMEVTYPER1	0x0000013E84	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB3_PMEVTYPER2	0x0000013E88	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB3_PMEVTYPER3	0x0000013E8C	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB3_PMCFGR	0x0000013F00	32	roRead-only	0x00011F03	Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data.
SMMU_CB3_PMCR	0x0000013F04	32	mixedMixed types. See bit-field details.	0x00000000	Provides the equivalent of the PMCR register, in the register map of a translation context bank. PMCR provides controls for the Performance Monitors.
SMMU_CB3_PMCEID	0x0000013F20	32	roRead-only	0x00030303	Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register, in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation.
SMMU_CB3_PMCNTENSE	0x0000013F40	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENSETx register, in the register map of a translation context bank. Enables any implemented event counters.
SMMU_CB3_PMCNTENCLR	0x0000013F44	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENCLRx register, in the register map of a translation context bank. Disables any implemented event counter.
SMMU_CB3_PMCNTENSET	0x0000013F48	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter
SMMU_CB3_PMINTENCLR	0x0000013F4C	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter.
SMMU_CB3_PMOVSCLR	0x0000013F50	32	woWrite-only	0x00000000	Provides the equivalent of the PMOVSCLRx register, in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter.
SMMU_CB3_PMOVSSET	0x0000013F58	32	woWrite-only	0x00000000	Provides the equivalent of PMOVSSETx, in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters.
smmu_cb3_pmauthstatus	0x0000013FB8	32	roRead-only	0x00000080	Provides the equivalent of the PMAUTHSTATUS register, in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug permissions
SMMU_CB4_SCTLR	0x0000014000	32	mixedMixed types. See bit-field details.	0x00000100	The System Control register provides the top level control of the translation system for the related Context bank.
SMMU_CB4_ACTLR	0x0000014004	32	rwNormal read/write	0x00000003	The Auxillary Control register provides implementation specific configuration and control options.
SMMU_CB4_RESUME	0x0000014008	32	woWrite-only	0x00000000	The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition.
SMMU_CB4_TCR2	0x0000014010	32	mixedMixed types. See bit-field details.	0x00000060	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB4_TTBR0_low	0x0000014020	32	mixedMixed types. See bit-field details.	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB4_TTBR0_high	0x0000014024	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB4_TTBR1_low	0x0000014028	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB4_TTBR1_high	0x000001402C	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB4_TCR_lpae	0x0000014030	32	rwNormal read/write	0x00000000	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB4_CONTEXTIDR	0x0000014034	32	rwNormal read/write	0x00000000	Identifies the current process identifier and the current address space identifier
SMMU_CB4_PRRR_MAIR0	0x0000014038	32	rwNormal read/write	0x00000000	Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX, C, and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB4_NMRR_MAIR1	0x000001403C	32	rwNormal read/write	0x00000000	Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB4_FSR	0x0000014058	32	woWrite-only	0x00000000	Provides memory system fault status information.
SMMU_CB4_FSRRESTORE	0x000001405C	32	woWrite-only	0x00000000	Restores the state of SMMU_CBn_FSR, after a reset, for example.
SMMU_CB4_FAR_low	0x0000014060	32	rwNormal read/write	0x00000000	Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception.
SMMU_CB4_FAR_high	0x0000014064	32	rwNormal read/write	0x00000000	Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception.
SMMU_CB4_FSYNR0	0x0000014068	32	mixedMixed types. See bit-field details.	0x00000000	Holds fault syndrome information about the memory access that caused a synchronous abort exception
SMMU_CB4_IPAFAR_low	0x0000014070	32	mixedMixed types. See bit-field details.	0x00000000	The stage 1 IPA Fault Address Lower bits [31:0] Register.
SMMU_CB4_IPAFAR_high	0x0000014074	32	rwNormal read/write	0x00000000	The stage 1 IPA Fault Address Upper bits [63:32] Register
SMMU_CB4_TLBIVA_low	0x0000014600	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate.
SMMU_CB4_TLBIVA_high	0x0000014604	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate
SMMU_CB4_TLBIVAA_low	0x0000014608	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB4_TLBIVAA_high	0x000001460C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB4_TLBIASID	0x0000014610	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the ASID provided as an argument
SMMU_CB4_TLBIALL	0x0000014618	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor, for HYPC banks, ii)Non-secure, using the VMID of the context bank, for Non-secure, non-HYPC context banks,iii) Secure, using any ASID, for Secure context banks.
SMMU_CB4_TLBIVAL_low	0x0000014620	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB4_TLBIVAL_high	0x0000014624	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB4_TLBIVAAL_low	0x0000014628	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB4_TLBIVAAL_high	0x000001462C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB4_TLBIIPAS2_low	0x0000014630	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB4_TLBIIPAS2_high	0x0000014634	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB4_TLBIIPAS2L_low	0x0000014638	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB4_TLBIIPAS2L_high	0x000001463C	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB4_TLBSYNC	0x00000147F0	32	woWrite-only	0x00000000	Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank.
SMMU_CB4_TLBSTATUS	0x00000147F4	32	roRead-only	0x00000000	Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation
SMMU_CB4_PMEVCNTR0	0x0000014E00	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB4_PMEVCNTR1	0x0000014E04	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB4_PMEVCNTR2	0x0000014E08	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB4_PMEVCNTR3	0x0000014E0C	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB4_PMEVTYPER0	0x0000014E80	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB4_PMEVTYPER1	0x0000014E84	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB4_PMEVTYPER2	0x0000014E88	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB4_PMEVTYPER3	0x0000014E8C	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB4_PMCFGR	0x0000014F00	32	roRead-only	0x00011F03	Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data.
SMMU_CB4_PMCR	0x0000014F04	32	mixedMixed types. See bit-field details.	0x00000000	Provides the equivalent of the PMCR register, in the register map of a translation context bank. PMCR provides controls for the Performance Monitors.
SMMU_CB4_PMCEID	0x0000014F20	32	roRead-only	0x00030303	Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register, in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation.
SMMU_CB4_PMCNTENSE	0x0000014F40	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENSETx register, in the register map of a translation context bank. Enables any implemented event counters.
SMMU_CB4_PMCNTENCLR	0x0000014F44	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENCLRx register, in the register map of a translation context bank. Disables any implemented event counter.
SMMU_CB4_PMCNTENSET	0x0000014F48	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter
SMMU_CB4_PMINTENCLR	0x0000014F4C	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter.
SMMU_CB4_PMOVSCLR	0x0000014F50	32	woWrite-only	0x00000000	Provides the equivalent of the PMOVSCLRx register, in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter.
SMMU_CB4_PMOVSSET	0x0000014F58	32	woWrite-only	0x00000000	Provides the equivalent of PMOVSSETx, in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters.
smmu_cb4_pmauthstatus	0x0000014FB8	32	roRead-only	0x00000080	Provides the equivalent of the PMAUTHSTATUS register, in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug permissions
SMMU_CB5_SCTLR	0x0000015000	32	mixedMixed types. See bit-field details.	0x00000100	The System Control register provides the top level control of the translation system for the related Context bank.
SMMU_CB5_ACTLR	0x0000015004	32	rwNormal read/write	0x00000003	The Auxillary Control register provides implementation specific configuration and control options.
SMMU_CB5_RESUME	0x0000015008	32	woWrite-only	0x00000000	The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition.
SMMU_CB5_TCR2	0x0000015010	32	mixedMixed types. See bit-field details.	0x00000060	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB5_TTBR0_low	0x0000015020	32	mixedMixed types. See bit-field details.	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB5_TTBR0_high	0x0000015024	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB5_TTBR1_low	0x0000015028	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB5_TTBR1_high	0x000001502C	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB5_TCR_lpae	0x0000015030	32	rwNormal read/write	0x00000000	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB5_CONTEXTIDR	0x0000015034	32	rwNormal read/write	0x00000000	Identifies the current process identifier and the current address space identifier
SMMU_CB5_PRRR_MAIR0	0x0000015038	32	rwNormal read/write	0x00000000	Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX, C, and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB5_NMRR_MAIR1	0x000001503C	32	rwNormal read/write	0x00000000	Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB5_FSR	0x0000015058	32	woWrite-only	0x00000000	Provides memory system fault status information.
SMMU_CB5_FSRRESTORE	0x000001505C	32	woWrite-only	0x00000000	Restores the state of SMMU_CBn_FSR, after a reset, for example.
SMMU_CB5_FAR_low	0x0000015060	32	rwNormal read/write	0x00000000	Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception.
SMMU_CB5_FAR_high	0x0000015064	32	rwNormal read/write	0x00000000	Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception.
SMMU_CB5_FSYNR0	0x0000015068	32	mixedMixed types. See bit-field details.	0x00000000	Holds fault syndrome information about the memory access that caused a synchronous abort exception
SMMU_CB5_IPAFAR_low	0x0000015070	32	mixedMixed types. See bit-field details.	0x00000000	The stage 1 IPA Fault Address Lower bits [31:0] Register.
SMMU_CB5_IPAFAR_high	0x0000015074	32	rwNormal read/write	0x00000000	The stage 1 IPA Fault Address Upper bits [63:32] Register
SMMU_CB5_TLBIVA_low	0x0000015600	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate.
SMMU_CB5_TLBIVA_high	0x0000015604	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate
SMMU_CB5_TLBIVAA_low	0x0000015608	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB5_TLBIVAA_high	0x000001560C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB5_TLBIASID	0x0000015610	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the ASID provided as an argument
SMMU_CB5_TLBIALL	0x0000015618	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor, for HYPC banks, ii)Non-secure, using the VMID of the context bank, for Non-secure, non-HYPC context banks,iii) Secure, using any ASID, for Secure context banks.
SMMU_CB5_TLBIVAL_low	0x0000015620	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB5_TLBIVAL_high	0x0000015624	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB5_TLBIVAAL_low	0x0000015628	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB5_TLBIVAAL_high	0x000001562C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB5_TLBIIPAS2_low	0x0000015630	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB5_TLBIIPAS2_high	0x0000015634	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB5_TLBIIPAS2L_low	0x0000015638	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB5_TLBIIPAS2L_high	0x000001563C	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB5_TLBSYNC	0x00000157F0	32	woWrite-only	0x00000000	Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank.
SMMU_CB5_TLBSTATUS	0x00000157F4	32	roRead-only	0x00000000	Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation
SMMU_CB5_PMEVCNTR0	0x0000015E00	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB5_PMEVCNTR1	0x0000015E04	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB5_PMEVCNTR2	0x0000015E08	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB5_PMEVCNTR3	0x0000015E0C	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB5_PMEVTYPER0	0x0000015E80	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB5_PMEVTYPER1	0x0000015E84	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB5_PMEVTYPER2	0x0000015E88	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB5_PMEVTYPER3	0x0000015E8C	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB5_PMCFGR	0x0000015F00	32	roRead-only	0x00011F03	Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data.
SMMU_CB5_PMCR	0x0000015F04	32	mixedMixed types. See bit-field details.	0x00000000	Provides the equivalent of the PMCR register, in the register map of a translation context bank. PMCR provides controls for the Performance Monitors.
SMMU_CB5_PMCEID	0x0000015F20	32	roRead-only	0x00030303	Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register, in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation.
SMMU_CB5_PMCNTENSE	0x0000015F40	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENSETx register, in the register map of a translation context bank. Enables any implemented event counters.
SMMU_CB5_PMCNTENCLR	0x0000015F44	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENCLRx register, in the register map of a translation context bank. Disables any implemented event counter.
SMMU_CB5_PMCNTENSET	0x0000015F48	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter
SMMU_CB5_PMINTENCLR	0x0000015F4C	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter.
SMMU_CB5_PMOVSCLR	0x0000015F50	32	woWrite-only	0x00000000	Provides the equivalent of the PMOVSCLRx register, in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter.
SMMU_CB5_PMOVSSET	0x0000015F58	32	woWrite-only	0x00000000	Provides the equivalent of PMOVSSETx, in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters.
smmu_cb5_pmauthstatus	0x0000015FB8	32	roRead-only	0x00000080	Provides the equivalent of the PMAUTHSTATUS register, in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug permissions
SMMU_CB6_SCTLR	0x0000016000	32	mixedMixed types. See bit-field details.	0x00000100	The System Control register provides the top level control of the translation system for the related Context bank.
SMMU_CB6_ACTLR	0x0000016004	32	rwNormal read/write	0x00000003	The Auxillary Control register provides implementation specific configuration and control options.
SMMU_CB6_RESUME	0x0000016008	32	woWrite-only	0x00000000	The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition.
SMMU_CB6_TCR2	0x0000016010	32	mixedMixed types. See bit-field details.	0x00000060	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB6_TTBR0_low	0x0000016020	32	mixedMixed types. See bit-field details.	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB6_TTBR0_high	0x0000016024	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB6_TTBR1_low	0x0000016028	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB6_TTBR1_high	0x000001602C	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB6_TCR_lpae	0x0000016030	32	rwNormal read/write	0x00000000	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB6_CONTEXTIDR	0x0000016034	32	rwNormal read/write	0x00000000	Identifies the current process identifier and the current address space identifier
SMMU_CB6_PRRR_MAIR0	0x0000016038	32	rwNormal read/write	0x00000000	Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX, C, and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB6_NMRR_MAIR1	0x000001603C	32	rwNormal read/write	0x00000000	Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB6_FSR	0x0000016058	32	woWrite-only	0x00000000	Provides memory system fault status information.
SMMU_CB6_FSRRESTORE	0x000001605C	32	woWrite-only	0x00000000	Restores the state of SMMU_CBn_FSR, after a reset, for example.
SMMU_CB6_FAR_low	0x0000016060	32	rwNormal read/write	0x00000000	Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception.
SMMU_CB6_FAR_high	0x0000016064	32	rwNormal read/write	0x00000000	Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception.
SMMU_CB6_FSYNR0	0x0000016068	32	mixedMixed types. See bit-field details.	0x00000000	Holds fault syndrome information about the memory access that caused a synchronous abort exception
SMMU_CB6_IPAFAR_low	0x0000016070	32	mixedMixed types. See bit-field details.	0x00000000	The stage 1 IPA Fault Address Lower bits [31:0] Register.
SMMU_CB6_IPAFAR_high	0x0000016074	32	rwNormal read/write	0x00000000	The stage 1 IPA Fault Address Upper bits [63:32] Register
SMMU_CB6_TLBIVA_low	0x0000016600	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate.
SMMU_CB6_TLBIVA_high	0x0000016604	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate
SMMU_CB6_TLBIVAA_low	0x0000016608	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB6_TLBIVAA_high	0x000001660C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB6_TLBIASID	0x0000016610	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the ASID provided as an argument
SMMU_CB6_TLBIALL	0x0000016618	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor, for HYPC banks, ii)Non-secure, using the VMID of the context bank, for Non-secure, non-HYPC context banks,iii) Secure, using any ASID, for Secure context banks.
SMMU_CB6_TLBIVAL_low	0x0000016620	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB6_TLBIVAL_high	0x0000016624	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB6_TLBIVAAL_low	0x0000016628	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB6_TLBIVAAL_high	0x000001662C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB6_TLBIIPAS2_low	0x0000016630	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB6_TLBIIPAS2_high	0x0000016634	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB6_TLBIIPAS2L_low	0x0000016638	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB6_TLBIIPAS2L_high	0x000001663C	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB6_TLBSYNC	0x00000167F0	32	woWrite-only	0x00000000	Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank.
SMMU_CB6_TLBSTATUS	0x00000167F4	32	roRead-only	0x00000000	Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation
SMMU_CB6_PMEVCNTR0	0x0000016E00	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB6_PMEVCNTR1	0x0000016E04	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB6_PMEVCNTR2	0x0000016E08	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB6_PMEVCNTR3	0x0000016E0C	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB6_PMEVTYPER0	0x0000016E80	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB6_PMEVTYPER1	0x0000016E84	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB6_PMEVTYPER2	0x0000016E88	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB6_PMEVTYPER3	0x0000016E8C	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB6_PMCFGR	0x0000016F00	32	roRead-only	0x00011F03	Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data.
SMMU_CB6_PMCR	0x0000016F04	32	mixedMixed types. See bit-field details.	0x00000000	Provides the equivalent of the PMCR register, in the register map of a translation context bank. PMCR provides controls for the Performance Monitors.
SMMU_CB6_PMCEID	0x0000016F20	32	roRead-only	0x00030303	Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register, in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation.
SMMU_CB6_PMCNTENSE	0x0000016F40	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENSETx register, in the register map of a translation context bank. Enables any implemented event counters.
SMMU_CB6_PMCNTENCLR	0x0000016F44	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENCLRx register, in the register map of a translation context bank. Disables any implemented event counter.
SMMU_CB6_PMCNTENSET	0x0000016F48	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter
SMMU_CB6_PMINTENCLR	0x0000016F4C	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter.
SMMU_CB6_PMOVSCLR	0x0000016F50	32	woWrite-only	0x00000000	Provides the equivalent of the PMOVSCLRx register, in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter.
SMMU_CB6_PMOVSSET	0x0000016F58	32	woWrite-only	0x00000000	Provides the equivalent of PMOVSSETx, in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters.
smmu_cb6_pmauthstatus	0x0000016FB8	32	roRead-only	0x00000080	Provides the equivalent of the PMAUTHSTATUS register, in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug permissions
SMMU_CB7_SCTLR	0x0000017000	32	mixedMixed types. See bit-field details.	0x00000100	The System Control register provides the top level control of the translation system for the related Context bank.
SMMU_CB7_ACTLR	0x0000017004	32	rwNormal read/write	0x00000003	The Auxillary Control register provides implementation specific configuration and control options.
SMMU_CB7_RESUME	0x0000017008	32	woWrite-only	0x00000000	The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition.
SMMU_CB7_TCR2	0x0000017010	32	mixedMixed types. See bit-field details.	0x00000060	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB7_TTBR0_low	0x0000017020	32	mixedMixed types. See bit-field details.	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB7_TTBR0_high	0x0000017024	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB7_TTBR1_low	0x0000017028	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB7_TTBR1_high	0x000001702C	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB7_TCR_lpae	0x0000017030	32	rwNormal read/write	0x00000000	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB7_CONTEXTIDR	0x0000017034	32	rwNormal read/write	0x00000000	Identifies the current process identifier and the current address space identifier
SMMU_CB7_PRRR_MAIR0	0x0000017038	32	rwNormal read/write	0x00000000	Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX, C, and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB7_NMRR_MAIR1	0x000001703C	32	rwNormal read/write	0x00000000	Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB7_FSR	0x0000017058	32	woWrite-only	0x00000000	Provides memory system fault status information.
SMMU_CB7_FSRRESTORE	0x000001705C	32	woWrite-only	0x00000000	Restores the state of SMMU_CBn_FSR, after a reset, for example.
SMMU_CB7_FAR_low	0x0000017060	32	rwNormal read/write	0x00000000	Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception.
SMMU_CB7_FAR_high	0x0000017064	32	rwNormal read/write	0x00000000	Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception.
SMMU_CB7_FSYNR0	0x0000017068	32	mixedMixed types. See bit-field details.	0x00000000	Holds fault syndrome information about the memory access that caused a synchronous abort exception
SMMU_CB7_IPAFAR_low	0x0000017070	32	mixedMixed types. See bit-field details.	0x00000000	The stage 1 IPA Fault Address Lower bits [31:0] Register.
SMMU_CB7_IPAFAR_high	0x0000017074	32	rwNormal read/write	0x00000000	The stage 1 IPA Fault Address Upper bits [63:32] Register
SMMU_CB7_TLBIVA_low	0x0000017600	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate.
SMMU_CB7_TLBIVA_high	0x0000017604	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate
SMMU_CB7_TLBIVAA_low	0x0000017608	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB7_TLBIVAA_high	0x000001760C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB7_TLBIASID	0x0000017610	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the ASID provided as an argument
SMMU_CB7_TLBIALL	0x0000017618	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor, for HYPC banks, ii)Non-secure, using the VMID of the context bank, for Non-secure, non-HYPC context banks,iii) Secure, using any ASID, for Secure context banks.
SMMU_CB7_TLBIVAL_low	0x0000017620	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB7_TLBIVAL_high	0x0000017624	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB7_TLBIVAAL_low	0x0000017628	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB7_TLBIVAAL_high	0x000001762C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB7_TLBIIPAS2_low	0x0000017630	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB7_TLBIIPAS2_high	0x0000017634	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB7_TLBIIPAS2L_low	0x0000017638	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB7_TLBIIPAS2L_high	0x000001763C	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB7_TLBSYNC	0x00000177F0	32	woWrite-only	0x00000000	Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank.
SMMU_CB7_TLBSTATUS	0x00000177F4	32	roRead-only	0x00000000	Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation
SMMU_CB7_PMEVCNTR0	0x0000017E00	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB7_PMEVCNTR1	0x0000017E04	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB7_PMEVCNTR2	0x0000017E08	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB7_PMEVCNTR3	0x0000017E0C	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB7_PMEVTYPER0	0x0000017E80	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB7_PMEVTYPER1	0x0000017E84	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB7_PMEVTYPER2	0x0000017E88	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB7_PMEVTYPER3	0x0000017E8C	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB7_PMCFGR	0x0000017F00	32	roRead-only	0x00011F03	Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data.
SMMU_CB7_PMCR	0x0000017F04	32	mixedMixed types. See bit-field details.	0x00000000	Provides the equivalent of the PMCR register, in the register map of a translation context bank. PMCR provides controls for the Performance Monitors.
SMMU_CB7_PMCEID	0x0000017F20	32	roRead-only	0x00030303	Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register, in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation.
SMMU_CB7_PMCNTENSE	0x0000017F40	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENSETx register, in the register map of a translation context bank. Enables any implemented event counters.
SMMU_CB7_PMCNTENCLR	0x0000017F44	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENCLRx register, in the register map of a translation context bank. Disables any implemented event counter.
SMMU_CB7_PMCNTENSET	0x0000017F48	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter
SMMU_CB7_PMINTENCLR	0x0000017F4C	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter.
SMMU_CB7_PMOVSCLR	0x0000017F50	32	woWrite-only	0x00000000	Provides the equivalent of the PMOVSCLRx register, in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter.
SMMU_CB7_PMOVSSET	0x0000017F58	32	woWrite-only	0x00000000	Provides the equivalent of PMOVSSETx, in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters.
smmu_cb7_pmauthstatus	0x0000017FB8	32	roRead-only	0x00000080	Provides the equivalent of the PMAUTHSTATUS register, in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug permissions
SMMU_CB8_SCTLR	0x0000018000	32	mixedMixed types. See bit-field details.	0x00000100	The System Control register provides the top level control of the translation system for the related Context bank.
SMMU_CB8_ACTLR	0x0000018004	32	rwNormal read/write	0x00000003	The Auxillary Control register provides implementation specific configuration and control options.
SMMU_CB8_RESUME	0x0000018008	32	woWrite-only	0x00000000	The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition.
SMMU_CB8_TCR2	0x0000018010	32	mixedMixed types. See bit-field details.	0x00000060	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB8_TTBR0_low	0x0000018020	32	mixedMixed types. See bit-field details.	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB8_TTBR0_high	0x0000018024	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB8_TTBR1_low	0x0000018028	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB8_TTBR1_high	0x000001802C	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB8_TCR_lpae	0x0000018030	32	rwNormal read/write	0x00000000	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB8_CONTEXTIDR	0x0000018034	32	rwNormal read/write	0x00000000	Identifies the current process identifier and the current address space identifier
SMMU_CB8_PRRR_MAIR0	0x0000018038	32	rwNormal read/write	0x00000000	Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX, C, and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB8_NMRR_MAIR1	0x000001803C	32	rwNormal read/write	0x00000000	Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB8_FSR	0x0000018058	32	woWrite-only	0x00000000	Provides memory system fault status information.
SMMU_CB8_FSRRESTORE	0x000001805C	32	woWrite-only	0x00000000	Restores the state of SMMU_CBn_FSR, after a reset, for example.
SMMU_CB8_FAR_low	0x0000018060	32	rwNormal read/write	0x00000000	Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception.
SMMU_CB8_FAR_high	0x0000018064	32	rwNormal read/write	0x00000000	Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception.
SMMU_CB8_FSYNR0	0x0000018068	32	mixedMixed types. See bit-field details.	0x00000000	Holds fault syndrome information about the memory access that caused a synchronous abort exception
SMMU_CB8_IPAFAR_low	0x0000018070	32	mixedMixed types. See bit-field details.	0x00000000	The stage 1 IPA Fault Address Lower bits [31:0] Register.
SMMU_CB8_IPAFAR_high	0x0000018074	32	rwNormal read/write	0x00000000	The stage 1 IPA Fault Address Upper bits [63:32] Register
SMMU_CB8_TLBIVA_low	0x0000018600	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate.
SMMU_CB8_TLBIVA_high	0x0000018604	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate
SMMU_CB8_TLBIVAA_low	0x0000018608	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB8_TLBIVAA_high	0x000001860C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB8_TLBIASID	0x0000018610	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the ASID provided as an argument
SMMU_CB8_TLBIALL	0x0000018618	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor, for HYPC banks, ii)Non-secure, using the VMID of the context bank, for Non-secure, non-HYPC context banks,iii) Secure, using any ASID, for Secure context banks.
SMMU_CB8_TLBIVAL_low	0x0000018620	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB8_TLBIVAL_high	0x0000018624	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB8_TLBIVAAL_low	0x0000018628	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB8_TLBIVAAL_high	0x000001862C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB8_TLBIIPAS2_low	0x0000018630	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB8_TLBIIPAS2_high	0x0000018634	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB8_TLBIIPAS2L_low	0x0000018638	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB8_TLBIIPAS2L_high	0x000001863C	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB8_TLBSYNC	0x00000187F0	32	woWrite-only	0x00000000	Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank.
SMMU_CB8_TLBSTATUS	0x00000187F4	32	roRead-only	0x00000000	Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation
SMMU_CB8_PMEVCNTR0	0x0000018E00	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB8_PMEVCNTR1	0x0000018E04	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB8_PMEVCNTR2	0x0000018E08	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB8_PMEVCNTR3	0x0000018E0C	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB8_PMEVTYPER0	0x0000018E80	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB8_PMEVTYPER1	0x0000018E84	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB8_PMEVTYPER2	0x0000018E88	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB8_PMEVTYPER3	0x0000018E8C	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB8_PMCFGR	0x0000018F00	32	roRead-only	0x00011F03	Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data.
SMMU_CB8_PMCR	0x0000018F04	32	mixedMixed types. See bit-field details.	0x00000000	Provides the equivalent of the PMCR register, in the register map of a translation context bank. PMCR provides controls for the Performance Monitors.
SMMU_CB8_PMCEID	0x0000018F20	32	roRead-only	0x00030303	Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register, in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation.
SMMU_CB8_PMCNTENSE	0x0000018F40	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENSETx register, in the register map of a translation context bank. Enables any implemented event counters.
SMMU_CB8_PMCNTENCLR	0x0000018F44	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENCLRx register, in the register map of a translation context bank. Disables any implemented event counter.
SMMU_CB8_PMCNTENSET	0x0000018F48	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter
SMMU_CB8_PMINTENCLR	0x0000018F4C	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter.
SMMU_CB8_PMOVSCLR	0x0000018F50	32	woWrite-only	0x00000000	Provides the equivalent of the PMOVSCLRx register, in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter.
SMMU_CB8_PMOVSSET	0x0000018F58	32	woWrite-only	0x00000000	Provides the equivalent of PMOVSSETx, in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters.
smmu_cb8_pmauthstatus	0x0000018FB8	32	roRead-only	0x00000080	Provides the equivalent of the PMAUTHSTATUS register, in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug permissions
SMMU_CB9_SCTLR	0x0000019000	32	mixedMixed types. See bit-field details.	0x00000100	The System Control register provides the top level control of the translation system for the related Context bank.
SMMU_CB9_ACTLR	0x0000019004	32	rwNormal read/write	0x00000003	The Auxillary Control register provides implementation specific configuration and control options.
SMMU_CB9_RESUME	0x0000019008	32	woWrite-only	0x00000000	The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition.
SMMU_CB9_TCR2	0x0000019010	32	mixedMixed types. See bit-field details.	0x00000060	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB9_TTBR0_low	0x0000019020	32	mixedMixed types. See bit-field details.	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB9_TTBR0_high	0x0000019024	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB9_TTBR1_low	0x0000019028	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB9_TTBR1_high	0x000001902C	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB9_TCR_lpae	0x0000019030	32	rwNormal read/write	0x00000000	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB9_CONTEXTIDR	0x0000019034	32	rwNormal read/write	0x00000000	Identifies the current process identifier and the current address space identifier
SMMU_CB9_PRRR_MAIR0	0x0000019038	32	rwNormal read/write	0x00000000	Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX, C, and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB9_NMRR_MAIR1	0x000001903C	32	rwNormal read/write	0x00000000	Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB9_FSR	0x0000019058	32	woWrite-only	0x00000000	Provides memory system fault status information.
SMMU_CB9_FSRRESTORE	0x000001905C	32	woWrite-only	0x00000000	Restores the state of SMMU_CBn_FSR, after a reset, for example.
SMMU_CB9_FAR_low	0x0000019060	32	rwNormal read/write	0x00000000	Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception.
SMMU_CB9_FAR_high	0x0000019064	32	rwNormal read/write	0x00000000	Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception.
SMMU_CB9_FSYNR0	0x0000019068	32	mixedMixed types. See bit-field details.	0x00000000	Holds fault syndrome information about the memory access that caused a synchronous abort exception
SMMU_CB9_IPAFAR_low	0x0000019070	32	mixedMixed types. See bit-field details.	0x00000000	The stage 1 IPA Fault Address Lower bits [31:0] Register.
SMMU_CB9_IPAFAR_high	0x0000019074	32	rwNormal read/write	0x00000000	The stage 1 IPA Fault Address Upper bits [63:32] Register
SMMU_CB9_TLBIVA_low	0x0000019600	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate.
SMMU_CB9_TLBIVA_high	0x0000019604	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate
SMMU_CB9_TLBIVAA_low	0x0000019608	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB9_TLBIVAA_high	0x000001960C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB9_TLBIASID	0x0000019610	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the ASID provided as an argument
SMMU_CB9_TLBIALL	0x0000019618	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor, for HYPC banks, ii)Non-secure, using the VMID of the context bank, for Non-secure, non-HYPC context banks,iii) Secure, using any ASID, for Secure context banks.
SMMU_CB9_TLBIVAL_low	0x0000019620	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB9_TLBIVAL_high	0x0000019624	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB9_TLBIVAAL_low	0x0000019628	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB9_TLBIVAAL_high	0x000001962C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB9_TLBIIPAS2_low	0x0000019630	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB9_TLBIIPAS2_high	0x0000019634	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB9_TLBIIPAS2L_low	0x0000019638	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB9_TLBIIPAS2L_high	0x000001963C	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB9_TLBSYNC	0x00000197F0	32	woWrite-only	0x00000000	Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank.
SMMU_CB9_TLBSTATUS	0x00000197F4	32	roRead-only	0x00000000	Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation
SMMU_CB9_PMEVCNTR0	0x0000019E00	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB9_PMEVCNTR1	0x0000019E04	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB9_PMEVCNTR2	0x0000019E08	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB9_PMEVCNTR3	0x0000019E0C	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB9_PMEVTYPER0	0x0000019E80	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB9_PMEVTYPER1	0x0000019E84	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB9_PMEVTYPER2	0x0000019E88	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB9_PMEVTYPER3	0x0000019E8C	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB9_PMCFGR	0x0000019F00	32	roRead-only	0x00011F03	Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data.
SMMU_CB9_PMCR	0x0000019F04	32	mixedMixed types. See bit-field details.	0x00000000	Provides the equivalent of the PMCR register, in the register map of a translation context bank. PMCR provides controls for the Performance Monitors.
SMMU_CB9_PMCEID	0x0000019F20	32	roRead-only	0x00030303	Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register, in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation.
SMMU_CB9_PMCNTENSE	0x0000019F40	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENSETx register, in the register map of a translation context bank. Enables any implemented event counters.
SMMU_CB9_PMCNTENCLR	0x0000019F44	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENCLRx register, in the register map of a translation context bank. Disables any implemented event counter.
SMMU_CB9_PMCNTENSET	0x0000019F48	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter
SMMU_CB9_PMINTENCLR	0x0000019F4C	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter.
SMMU_CB9_PMOVSCLR	0x0000019F50	32	woWrite-only	0x00000000	Provides the equivalent of the PMOVSCLRx register, in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter.
SMMU_CB9_PMOVSSET	0x0000019F58	32	woWrite-only	0x00000000	Provides the equivalent of PMOVSSETx, in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters.
smmu_cb9_pmauthstatus	0x0000019FB8	32	roRead-only	0x00000080	Provides the equivalent of the PMAUTHSTATUS register, in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug permissions
SMMU_CB10_SCTLR	0x000001A000	32	mixedMixed types. See bit-field details.	0x00000100	The System Control register provides the top level control of the translation system for the related Context bank.
SMMU_CB10_ACTLR	0x000001A004	32	rwNormal read/write	0x00000003	The Auxillary Control register provides implementation specific configuration and control options.
SMMU_CB10_RESUME	0x000001A008	32	woWrite-only	0x00000000	The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition.
SMMU_CB10_TCR2	0x000001A010	32	mixedMixed types. See bit-field details.	0x00000060	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB10_TTBR0_low	0x000001A020	32	mixedMixed types. See bit-field details.	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB10_TTBR0_high	0x000001A024	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB10_TTBR1_low	0x000001A028	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB10_TTBR1_high	0x000001A02C	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB10_TCR_lpae	0x000001A030	32	rwNormal read/write	0x00000000	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB10_CONTEXTIDR	0x000001A034	32	rwNormal read/write	0x00000000	Identifies the current process identifier and the current address space identifier
SMMU_CB10_PRRR_MAIR0	0x000001A038	32	rwNormal read/write	0x00000000	Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX, C, and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB10_NMRR_MAIR1	0x000001A03C	32	rwNormal read/write	0x00000000	Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB10_FSR	0x000001A058	32	woWrite-only	0x00000000	Provides memory system fault status information.
SMMU_CB10_FSRRESTORE	0x000001A05C	32	woWrite-only	0x00000000	Restores the state of SMMU_CBn_FSR, after a reset, for example.
SMMU_CB10_FAR_low	0x000001A060	32	rwNormal read/write	0x00000000	Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception.
SMMU_CB10_FAR_high	0x000001A064	32	rwNormal read/write	0x00000000	Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception.
SMMU_CB10_FSYNR0	0x000001A068	32	mixedMixed types. See bit-field details.	0x00000000	Holds fault syndrome information about the memory access that caused a synchronous abort exception
SMMU_CB10_IPAFAR_low	0x000001A070	32	mixedMixed types. See bit-field details.	0x00000000	The stage 1 IPA Fault Address Lower bits [31:0] Register.
SMMU_CB10_IPAFAR_high	0x000001A074	32	rwNormal read/write	0x00000000	The stage 1 IPA Fault Address Upper bits [63:32] Register
SMMU_CB10_TLBIVA_low	0x000001A600	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate.
SMMU_CB10_TLBIVA_high	0x000001A604	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate
SMMU_CB10_TLBIVAA_low	0x000001A608	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB10_TLBIVAA_high	0x000001A60C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB10_TLBIASID	0x000001A610	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the ASID provided as an argument
SMMU_CB10_TLBIALL	0x000001A618	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor, for HYPC banks, ii)Non-secure, using the VMID of the context bank, for Non-secure, non-HYPC context banks,iii) Secure, using any ASID, for Secure context banks.
SMMU_CB10_TLBIVAL_low	0x000001A620	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB10_TLBIVAL_high	0x000001A624	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB10_TLBIVAAL_low	0x000001A628	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB10_TLBIVAAL_high	0x000001A62C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB10_TLBIIPAS2_low	0x000001A630	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB10_TLBIIPAS2_high	0x000001A634	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB10_TLBIIPAS2L_low	0x000001A638	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB10_TLBIIPAS2L_high	0x000001A63C	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB10_TLBSYNC	0x000001A7F0	32	woWrite-only	0x00000000	Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank.
SMMU_CB10_TLBSTATUS	0x000001A7F4	32	roRead-only	0x00000000	Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation
SMMU_CB10_PMEVCNTR0	0x000001AE00	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB10_PMEVCNTR1	0x000001AE04	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB10_PMEVCNTR2	0x000001AE08	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB10_PMEVCNTR3	0x000001AE0C	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB10_PMEVTYPER0	0x000001AE80	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB10_PMEVTYPER1	0x000001AE84	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB10_PMEVTYPER2	0x000001AE88	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB10_PMEVTYPER3	0x000001AE8C	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB10_PMCFGR	0x000001AF00	32	roRead-only	0x00011F03	Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data.
SMMU_CB10_PMCR	0x000001AF04	32	mixedMixed types. See bit-field details.	0x00000000	Provides the equivalent of the PMCR register, in the register map of a translation context bank. PMCR provides controls for the Performance Monitors.
SMMU_CB10_PMCEID	0x000001AF20	32	roRead-only	0x00030303	Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register, in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation.
SMMU_CB10_PMCNTENSE	0x000001AF40	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENSETx register, in the register map of a translation context bank. Enables any implemented event counters.
SMMU_CB10_PMCNTENCLR	0x000001AF44	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENCLRx register, in the register map of a translation context bank. Disables any implemented event counter.
SMMU_CB10_PMCNTENSET	0x000001AF48	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter
SMMU_CB10_PMINTENCLR	0x000001AF4C	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter.
SMMU_CB10_PMOVSCLR	0x000001AF50	32	woWrite-only	0x00000000	Provides the equivalent of the PMOVSCLRx register, in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter.
SMMU_CB10_PMOVSSET	0x000001AF58	32	woWrite-only	0x00000000	Provides the equivalent of PMOVSSETx, in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters.
smmu_cb10_pmauthstatus	0x000001AFB8	32	roRead-only	0x00000080	Provides the equivalent of the PMAUTHSTATUS register, in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug permissions
SMMU_CB11_SCTLR	0x000001B000	32	mixedMixed types. See bit-field details.	0x00000100	The System Control register provides the top level control of the translation system for the related Context bank.
SMMU_CB11_ACTLR	0x000001B004	32	rwNormal read/write	0x00000003	The Auxillary Control register provides implementation specific configuration and control options.
SMMU_CB11_RESUME	0x000001B008	32	woWrite-only	0x00000000	The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition.
SMMU_CB11_TCR2	0x000001B010	32	mixedMixed types. See bit-field details.	0x00000060	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB11_TTBR0_low	0x000001B020	32	mixedMixed types. See bit-field details.	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB11_TTBR0_high	0x000001B024	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB11_TTBR1_low	0x000001B028	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB11_TTBR1_high	0x000001B02C	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB11_TCR_lpae	0x000001B030	32	rwNormal read/write	0x00000000	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB11_CONTEXTIDR	0x000001B034	32	rwNormal read/write	0x00000000	Identifies the current process identifier and the current address space identifier
SMMU_CB11_PRRR_MAIR0	0x000001B038	32	rwNormal read/write	0x00000000	Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX, C, and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB11_NMRR_MAIR1	0x000001B03C	32	rwNormal read/write	0x00000000	Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB11_FSR	0x000001B058	32	woWrite-only	0x00000000	Provides memory system fault status information.
SMMU_CB11_FSRRESTORE	0x000001B05C	32	woWrite-only	0x00000000	Restores the state of SMMU_CBn_FSR, after a reset, for example.
SMMU_CB11_FAR_low	0x000001B060	32	rwNormal read/write	0x00000000	Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception.
SMMU_CB11_FAR_high	0x000001B064	32	rwNormal read/write	0x00000000	Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception.
SMMU_CB11_FSYNR0	0x000001B068	32	mixedMixed types. See bit-field details.	0x00000000	Holds fault syndrome information about the memory access that caused a synchronous abort exception
SMMU_CB11_IPAFAR_low	0x000001B070	32	mixedMixed types. See bit-field details.	0x00000000	The stage 1 IPA Fault Address Lower bits [31:0] Register.
SMMU_CB11_IPAFAR_high	0x000001B074	32	rwNormal read/write	0x00000000	The stage 1 IPA Fault Address Upper bits [63:32] Register
SMMU_CB11_TLBIVA_low	0x000001B600	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate.
SMMU_CB11_TLBIVA_high	0x000001B604	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate
SMMU_CB11_TLBIVAA_low	0x000001B608	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB11_TLBIVAA_high	0x000001B60C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB11_TLBIASID	0x000001B610	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the ASID provided as an argument
SMMU_CB11_TLBIALL	0x000001B618	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor, for HYPC banks, ii)Non-secure, using the VMID of the context bank, for Non-secure, non-HYPC context banks,iii) Secure, using any ASID, for Secure context banks.
SMMU_CB11_TLBIVAL_low	0x000001B620	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB11_TLBIVAL_high	0x000001B624	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB11_TLBIVAAL_low	0x000001B628	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB11_TLBIVAAL_high	0x000001B62C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB11_TLBIIPAS2_low	0x000001B630	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB11_TLBIIPAS2_high	0x000001B634	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB11_TLBIIPAS2L_low	0x000001B638	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB11_TLBIIPAS2L_high	0x000001B63C	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB11_TLBSYNC	0x000001B7F0	32	woWrite-only	0x00000000	Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank.
SMMU_CB11_TLBSTATUS	0x000001B7F4	32	roRead-only	0x00000000	Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation
SMMU_CB11_PMEVCNTR0	0x000001BE00	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB11_PMEVCNTR1	0x000001BE04	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB11_PMEVCNTR2	0x000001BE08	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB11_PMEVCNTR3	0x000001BE0C	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB11_PMEVTYPER0	0x000001BE80	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB11_PMEVTYPER1	0x000001BE84	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB11_PMEVTYPER2	0x000001BE88	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB11_PMEVTYPER3	0x000001BE8C	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB11_PMCFGR	0x000001BF00	32	roRead-only	0x00011F03	Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data.
SMMU_CB11_PMCR	0x000001BF04	32	mixedMixed types. See bit-field details.	0x00000000	Provides the equivalent of the PMCR register, in the register map of a translation context bank. PMCR provides controls for the Performance Monitors.
SMMU_CB11_PMCEID	0x000001BF20	32	roRead-only	0x00030303	Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register, in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation.
SMMU_CB11_PMCNTENSE	0x000001BF40	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENSETx register, in the register map of a translation context bank. Enables any implemented event counters.
SMMU_CB11_PMCNTENCLR	0x000001BF44	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENCLRx register, in the register map of a translation context bank. Disables any implemented event counter.
SMMU_CB11_PMCNTENSET	0x000001BF48	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter
SMMU_CB11_PMINTENCLR	0x000001BF4C	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter.
SMMU_CB11_PMOVSCLR	0x000001BF50	32	woWrite-only	0x00000000	Provides the equivalent of the PMOVSCLRx register, in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter.
SMMU_CB11_PMOVSSET	0x000001BF58	32	woWrite-only	0x00000000	Provides the equivalent of PMOVSSETx, in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters.
smmu_cb11_pmauthstatus	0x000001BFB8	32	roRead-only	0x00000080	Provides the equivalent of the PMAUTHSTATUS register, in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug permissions
SMMU_CB12_SCTLR	0x000001C000	32	mixedMixed types. See bit-field details.	0x00000100	The System Control register provides the top level control of the translation system for the related Context bank.
SMMU_CB12_ACTLR	0x000001C004	32	rwNormal read/write	0x00000003	The Auxillary Control register provides implementation specific configuration and control options.
SMMU_CB12_RESUME	0x000001C008	32	woWrite-only	0x00000000	The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition.
SMMU_CB12_TCR2	0x000001C010	32	mixedMixed types. See bit-field details.	0x00000060	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB12_TTBR0_low	0x000001C020	32	mixedMixed types. See bit-field details.	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB12_TTBR0_high	0x000001C024	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB12_TTBR1_low	0x000001C028	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB12_TTBR1_high	0x000001C02C	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB12_TCR_lpae	0x000001C030	32	rwNormal read/write	0x00000000	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB12_CONTEXTIDR	0x000001C034	32	rwNormal read/write	0x00000000	Identifies the current process identifier and the current address space identifier
SMMU_CB12_PRRR_MAIR0	0x000001C038	32	rwNormal read/write	0x00000000	Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX, C, and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB12_NMRR_MAIR1	0x000001C03C	32	rwNormal read/write	0x00000000	Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB12_FSR	0x000001C058	32	woWrite-only	0x00000000	Provides memory system fault status information.
SMMU_CB12_FSRRESTORE	0x000001C05C	32	woWrite-only	0x00000000	Restores the state of SMMU_CBn_FSR, after a reset, for example.
SMMU_CB12_FAR_low	0x000001C060	32	rwNormal read/write	0x00000000	Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception.
SMMU_CB12_FAR_high	0x000001C064	32	rwNormal read/write	0x00000000	Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception.
SMMU_CB12_FSYNR0	0x000001C068	32	mixedMixed types. See bit-field details.	0x00000000	Holds fault syndrome information about the memory access that caused a synchronous abort exception
SMMU_CB12_IPAFAR_low	0x000001C070	32	mixedMixed types. See bit-field details.	0x00000000	The stage 1 IPA Fault Address Lower bits [31:0] Register.
SMMU_CB12_IPAFAR_high	0x000001C074	32	rwNormal read/write	0x00000000	The stage 1 IPA Fault Address Upper bits [63:32] Register
SMMU_CB12_TLBIVA_low	0x000001C600	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate.
SMMU_CB12_TLBIVA_high	0x000001C604	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate
SMMU_CB12_TLBIVAA_low	0x000001C608	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB12_TLBIVAA_high	0x000001C60C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB12_TLBIASID	0x000001C610	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the ASID provided as an argument
SMMU_CB12_TLBIALL	0x000001C618	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor, for HYPC banks, ii)Non-secure, using the VMID of the context bank, for Non-secure, non-HYPC context banks,iii) Secure, using any ASID, for Secure context banks.
SMMU_CB12_TLBIVAL_low	0x000001C620	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB12_TLBIVAL_high	0x000001C624	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB12_TLBIVAAL_low	0x000001C628	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB12_TLBIVAAL_high	0x000001C62C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB12_TLBIIPAS2_low	0x000001C630	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB12_TLBIIPAS2_high	0x000001C634	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB12_TLBIIPAS2L_low	0x000001C638	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB12_TLBIIPAS2L_high	0x000001C63C	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB12_TLBSYNC	0x000001C7F0	32	woWrite-only	0x00000000	Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank.
SMMU_CB12_TLBSTATUS	0x000001C7F4	32	roRead-only	0x00000000	Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation
SMMU_CB12_PMEVCNTR0	0x000001CE00	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB12_PMEVCNTR1	0x000001CE04	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB12_PMEVCNTR2	0x000001CE08	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB12_PMEVCNTR3	0x000001CE0C	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB12_PMEVTYPER0	0x000001CE80	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB12_PMEVTYPER1	0x000001CE84	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB12_PMEVTYPER2	0x000001CE88	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB12_PMEVTYPER3	0x000001CE8C	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB12_PMCFGR	0x000001CF00	32	roRead-only	0x00011F03	Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data.
SMMU_CB12_PMCR	0x000001CF04	32	mixedMixed types. See bit-field details.	0x00000000	Provides the equivalent of the PMCR register, in the register map of a translation context bank. PMCR provides controls for the Performance Monitors.
SMMU_CB12_PMCEID	0x000001CF20	32	roRead-only	0x00030303	Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register, in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation.
SMMU_CB12_PMCNTENSE	0x000001CF40	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENSETx register, in the register map of a translation context bank. Enables any implemented event counters.
SMMU_CB12_PMCNTENCLR	0x000001CF44	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENCLRx register, in the register map of a translation context bank. Disables any implemented event counter.
SMMU_CB12_PMCNTENSET	0x000001CF48	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter
SMMU_CB12_PMINTENCLR	0x000001CF4C	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter.
SMMU_CB12_PMOVSCLR	0x000001CF50	32	woWrite-only	0x00000000	Provides the equivalent of the PMOVSCLRx register, in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter.
SMMU_CB12_PMOVSSET	0x000001CF58	32	woWrite-only	0x00000000	Provides the equivalent of PMOVSSETx, in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters.
smmu_cb12_pmauthstatus	0x000001CFB8	32	roRead-only	0x00000080	Provides the equivalent of the PMAUTHSTATUS register, in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug permissions
SMMU_CB13_SCTLR	0x000001D000	32	mixedMixed types. See bit-field details.	0x00000100	The System Control register provides the top level control of the translation system for the related Context bank.
SMMU_CB13_ACTLR	0x000001D004	32	rwNormal read/write	0x00000003	The Auxillary Control register provides implementation specific configuration and control options.
SMMU_CB13_RESUME	0x000001D008	32	woWrite-only	0x00000000	The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition.
SMMU_CB13_TCR2	0x000001D010	32	mixedMixed types. See bit-field details.	0x00000060	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB13_TTBR0_low	0x000001D020	32	mixedMixed types. See bit-field details.	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB13_TTBR0_high	0x000001D024	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB13_TTBR1_low	0x000001D028	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB13_TTBR1_high	0x000001D02C	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB13_TCR_lpae	0x000001D030	32	rwNormal read/write	0x00000000	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB13_CONTEXTIDR	0x000001D034	32	rwNormal read/write	0x00000000	Identifies the current process identifier and the current address space identifier
SMMU_CB13_PRRR_MAIR0	0x000001D038	32	rwNormal read/write	0x00000000	Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX, C, and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB13_NMRR_MAIR1	0x000001D03C	32	rwNormal read/write	0x00000000	Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB13_FSR	0x000001D058	32	woWrite-only	0x00000000	Provides memory system fault status information.
SMMU_CB13_FSRRESTORE	0x000001D05C	32	woWrite-only	0x00000000	Restores the state of SMMU_CBn_FSR, after a reset, for example.
SMMU_CB13_FAR_low	0x000001D060	32	rwNormal read/write	0x00000000	Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception.
SMMU_CB13_FAR_high	0x000001D064	32	rwNormal read/write	0x00000000	Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception.
SMMU_CB13_FSYNR0	0x000001D068	32	mixedMixed types. See bit-field details.	0x00000000	Holds fault syndrome information about the memory access that caused a synchronous abort exception
SMMU_CB13_IPAFAR_low	0x000001D070	32	mixedMixed types. See bit-field details.	0x00000000	The stage 1 IPA Fault Address Lower bits [31:0] Register.
SMMU_CB13_IPAFAR_high	0x000001D074	32	rwNormal read/write	0x00000000	The stage 1 IPA Fault Address Upper bits [63:32] Register
SMMU_CB13_TLBIVA_low	0x000001D600	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate.
SMMU_CB13_TLBIVA_high	0x000001D604	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate
SMMU_CB13_TLBIVAA_low	0x000001D608	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB13_TLBIVAA_high	0x000001D60C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB13_TLBIASID	0x000001D610	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the ASID provided as an argument
SMMU_CB13_TLBIALL	0x000001D618	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor, for HYPC banks, ii)Non-secure, using the VMID of the context bank, for Non-secure, non-HYPC context banks,iii) Secure, using any ASID, for Secure context banks.
SMMU_CB13_TLBIVAL_low	0x000001D620	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB13_TLBIVAL_high	0x000001D624	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB13_TLBIVAAL_low	0x000001D628	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB13_TLBIVAAL_high	0x000001D62C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB13_TLBIIPAS2_low	0x000001D630	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB13_TLBIIPAS2_high	0x000001D634	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB13_TLBIIPAS2L_low	0x000001D638	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB13_TLBIIPAS2L_high	0x000001D63C	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB13_TLBSYNC	0x000001D7F0	32	woWrite-only	0x00000000	Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank.
SMMU_CB13_TLBSTATUS	0x000001D7F4	32	roRead-only	0x00000000	Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation
SMMU_CB13_PMEVCNTR0	0x000001DE00	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB13_PMEVCNTR1	0x000001DE04	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB13_PMEVCNTR2	0x000001DE08	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB13_PMEVCNTR3	0x000001DE0C	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB13_PMEVTYPER0	0x000001DE80	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB13_PMEVTYPER1	0x000001DE84	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB13_PMEVTYPER2	0x000001DE88	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB13_PMEVTYPER3	0x000001DE8C	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB13_PMCFGR	0x000001DF00	32	roRead-only	0x00011F03	Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data.
SMMU_CB13_PMCR	0x000001DF04	32	mixedMixed types. See bit-field details.	0x00000000	Provides the equivalent of the PMCR register, in the register map of a translation context bank. PMCR provides controls for the Performance Monitors.
SMMU_CB13_PMCEID	0x000001DF20	32	roRead-only	0x00030303	Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register, in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation.
SMMU_CB13_PMCNTENSE	0x000001DF40	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENSETx register, in the register map of a translation context bank. Enables any implemented event counters.
SMMU_CB13_PMCNTENCLR	0x000001DF44	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENCLRx register, in the register map of a translation context bank. Disables any implemented event counter.
SMMU_CB13_PMCNTENSET	0x000001DF48	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter
SMMU_CB13_PMINTENCLR	0x000001DF4C	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter.
SMMU_CB13_PMOVSCLR	0x000001DF50	32	woWrite-only	0x00000000	Provides the equivalent of the PMOVSCLRx register, in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter.
SMMU_CB13_PMOVSSET	0x000001DF58	32	woWrite-only	0x00000000	Provides the equivalent of PMOVSSETx, in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters.
smmu_cb13_pmauthstatus	0x000001DFB8	32	roRead-only	0x00000080	Provides the equivalent of the PMAUTHSTATUS register, in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug permissions
SMMU_CB14_SCTLR	0x000001E000	32	mixedMixed types. See bit-field details.	0x00000100	The System Control register provides the top level control of the translation system for the related Context bank.
SMMU_CB14_ACTLR	0x000001E004	32	rwNormal read/write	0x00000003	The Auxillary Control register provides implementation specific configuration and control options.
SMMU_CB14_RESUME	0x000001E008	32	woWrite-only	0x00000000	The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition.
SMMU_CB14_TCR2	0x000001E010	32	mixedMixed types. See bit-field details.	0x00000060	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB14_TTBR0_low	0x000001E020	32	mixedMixed types. See bit-field details.	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB14_TTBR0_high	0x000001E024	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB14_TTBR1_low	0x000001E028	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB14_TTBR1_high	0x000001E02C	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB14_TCR_lpae	0x000001E030	32	rwNormal read/write	0x00000000	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB14_CONTEXTIDR	0x000001E034	32	rwNormal read/write	0x00000000	Identifies the current process identifier and the current address space identifier
SMMU_CB14_PRRR_MAIR0	0x000001E038	32	rwNormal read/write	0x00000000	Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX, C, and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB14_NMRR_MAIR1	0x000001E03C	32	rwNormal read/write	0x00000000	Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB14_FSR	0x000001E058	32	woWrite-only	0x00000000	Provides memory system fault status information.
SMMU_CB14_FSRRESTORE	0x000001E05C	32	woWrite-only	0x00000000	Restores the state of SMMU_CBn_FSR, after a reset, for example.
SMMU_CB14_FAR_low	0x000001E060	32	rwNormal read/write	0x00000000	Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception.
SMMU_CB14_FAR_high	0x000001E064	32	rwNormal read/write	0x00000000	Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception.
SMMU_CB14_FSYNR0	0x000001E068	32	mixedMixed types. See bit-field details.	0x00000000	Holds fault syndrome information about the memory access that caused a synchronous abort exception
SMMU_CB14_IPAFAR_low	0x000001E070	32	mixedMixed types. See bit-field details.	0x00000000	The stage 1 IPA Fault Address Lower bits [31:0] Register.
SMMU_CB14_IPAFAR_high	0x000001E074	32	rwNormal read/write	0x00000000	The stage 1 IPA Fault Address Upper bits [63:32] Register
SMMU_CB14_TLBIVA_low	0x000001E600	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate.
SMMU_CB14_TLBIVA_high	0x000001E604	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate
SMMU_CB14_TLBIVAA_low	0x000001E608	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB14_TLBIVAA_high	0x000001E60C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB14_TLBIASID	0x000001E610	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the ASID provided as an argument
SMMU_CB14_TLBIALL	0x000001E618	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor, for HYPC banks, ii)Non-secure, using the VMID of the context bank, for Non-secure, non-HYPC context banks,iii) Secure, using any ASID, for Secure context banks.
SMMU_CB14_TLBIVAL_low	0x000001E620	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB14_TLBIVAL_high	0x000001E624	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB14_TLBIVAAL_low	0x000001E628	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB14_TLBIVAAL_high	0x000001E62C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB14_TLBIIPAS2_low	0x000001E630	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB14_TLBIIPAS2_high	0x000001E634	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB14_TLBIIPAS2L_low	0x000001E638	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB14_TLBIIPAS2L_high	0x000001E63C	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB14_TLBSYNC	0x000001E7F0	32	woWrite-only	0x00000000	Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank.
SMMU_CB14_TLBSTATUS	0x000001E7F4	32	roRead-only	0x00000000	Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation
SMMU_CB14_PMEVCNTR0	0x000001EE00	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB14_PMEVCNTR1	0x000001EE04	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB14_PMEVCNTR2	0x000001EE08	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB14_PMEVCNTR3	0x000001EE0C	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB14_PMEVTYPER0	0x000001EE80	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB14_PMEVTYPER1	0x000001EE84	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB14_PMEVTYPER2	0x000001EE88	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB14_PMEVTYPER3	0x000001EE8C	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB14_PMCFGR	0x000001EF00	32	roRead-only	0x00011F03	Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data.
SMMU_CB14_PMCR	0x000001EF04	32	mixedMixed types. See bit-field details.	0x00000000	Provides the equivalent of the PMCR register, in the register map of a translation context bank. PMCR provides controls for the Performance Monitors.
SMMU_CB14_PMCEID	0x000001EF20	32	roRead-only	0x00030303	Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register, in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation.
SMMU_CB14_PMCNTENSE	0x000001EF40	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENSETx register, in the register map of a translation context bank. Enables any implemented event counters.
SMMU_CB14_PMCNTENCLR	0x000001EF44	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENCLRx register, in the register map of a translation context bank. Disables any implemented event counter.
SMMU_CB14_PMCNTENSET	0x000001EF48	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter
SMMU_CB14_PMINTENCLR	0x000001EF4C	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter.
SMMU_CB14_PMOVSCLR	0x000001EF50	32	woWrite-only	0x00000000	Provides the equivalent of the PMOVSCLRx register, in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter.
SMMU_CB14_PMOVSSET	0x000001EF58	32	woWrite-only	0x00000000	Provides the equivalent of PMOVSSETx, in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters.
smmu_cb14_pmauthstatus	0x000001EFB8	32	roRead-only	0x00000080	Provides the equivalent of the PMAUTHSTATUS register, in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug permissions
SMMU_CB15_SCTLR	0x000001F000	32	mixedMixed types. See bit-field details.	0x00000100	The System Control register provides the top level control of the translation system for the related Context bank.
SMMU_CB15_ACTLR	0x000001F004	32	rwNormal read/write	0x00000003	The Auxillary Control register provides implementation specific configuration and control options.
SMMU_CB15_RESUME	0x000001F008	32	woWrite-only	0x00000000	The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition.
SMMU_CB15_TCR2	0x000001F010	32	mixedMixed types. See bit-field details.	0x00000060	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB15_TTBR0_low	0x000001F020	32	mixedMixed types. See bit-field details.	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB15_TTBR0_high	0x000001F024	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 0.
SMMU_CB15_TTBR1_low	0x000001F028	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB15_TTBR1_high	0x000001F02C	32	rwNormal read/write	0x00000000	The Translation Table Base register 0 holds the base address of the translation table 1.
SMMU_CB15_TCR_lpae	0x000001F030	32	rwNormal read/write	0x00000000	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
SMMU_CB15_CONTEXTIDR	0x000001F034	32	rwNormal read/write	0x00000000	Identifies the current process identifier and the current address space identifier
SMMU_CB15_PRRR_MAIR0	0x000001F038	32	rwNormal read/write	0x00000000	Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX, C, and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB15_NMRR_MAIR1	0x000001F03C	32	rwNormal read/write	0x00000000	Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
SMMU_CB15_FSR	0x000001F058	32	woWrite-only	0x00000000	Provides memory system fault status information.
SMMU_CB15_FSRRESTORE	0x000001F05C	32	woWrite-only	0x00000000	Restores the state of SMMU_CBn_FSR, after a reset, for example.
SMMU_CB15_FAR_low	0x000001F060	32	rwNormal read/write	0x00000000	Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception.
SMMU_CB15_FAR_high	0x000001F064	32	rwNormal read/write	0x00000000	Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception.
SMMU_CB15_FSYNR0	0x000001F068	32	mixedMixed types. See bit-field details.	0x00000000	Holds fault syndrome information about the memory access that caused a synchronous abort exception
SMMU_CB15_IPAFAR_low	0x000001F070	32	mixedMixed types. See bit-field details.	0x00000000	The stage 1 IPA Fault Address Lower bits [31:0] Register.
SMMU_CB15_IPAFAR_high	0x000001F074	32	rwNormal read/write	0x00000000	The stage 1 IPA Fault Address Upper bits [63:32] Register
SMMU_CB15_TLBIVA_low	0x000001F600	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate.
SMMU_CB15_TLBIVA_high	0x000001F604	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank, including any global entries if appropriate
SMMU_CB15_TLBIVAA_low	0x000001F608	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB15_TLBIVAA_high	0x000001F60C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.
SMMU_CB15_TLBIASID	0x000001F610	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the ASID provided as an argument
SMMU_CB15_TLBIALL	0x000001F618	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor, for HYPC banks, ii)Non-secure, using the VMID of the context bank, for Non-secure, non-HYPC context banks,iii) Secure, using any ASID, for Secure context banks.
SMMU_CB15_TLBIVAL_low	0x000001F620	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB15_TLBIVAL_high	0x000001F624	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.
SMMU_CB15_TLBIVAAL_low	0x000001F628	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB15_TLBIVAAL_high	0x000001F62C	32	woWrite-only	0x00000000	Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation
SMMU_CB15_TLBIIPAS2_low	0x000001F630	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB15_TLBIIPAS2_high	0x000001F634	32	woWrite-only	0x00000000	Invalidates all unlocked TLB entries that match the IPA provided
SMMU_CB15_TLBIIPAS2L_low	0x000001F638	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB15_TLBIIPAS2L_high	0x000001F63C	32	woWrite-only	0x00000000	Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup
SMMU_CB15_TLBSYNC	0x000001F7F0	32	woWrite-only	0x00000000	Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank.
SMMU_CB15_TLBSTATUS	0x000001F7F4	32	roRead-only	0x00000000	Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation
SMMU_CB15_PMEVCNTR0	0x000001FE00	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB15_PMEVCNTR1	0x000001FE04	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB15_PMEVCNTR2	0x000001FE08	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB15_PMEVCNTR3	0x000001FE0C	32	rwNormal read/write	0x00000000	Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.
SMMU_CB15_PMEVTYPER0	0x000001FE80	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB15_PMEVTYPER1	0x000001FE84	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB15_PMEVTYPER2	0x000001FE88	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB15_PMEVTYPER3	0x000001FE8C	32	rwNormal read/write	0x00000000	Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter
SMMU_CB15_PMCFGR	0x000001FF00	32	roRead-only	0x00011F03	Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data.
SMMU_CB15_PMCR	0x000001FF04	32	mixedMixed types. See bit-field details.	0x00000000	Provides the equivalent of the PMCR register, in the register map of a translation context bank. PMCR provides controls for the Performance Monitors.
SMMU_CB15_PMCEID	0x000001FF20	32	roRead-only	0x00030303	Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register, in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation.
SMMU_CB15_PMCNTENSE	0x000001FF40	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENSETx register, in the register map of a translation context bank. Enables any implemented event counters.
SMMU_CB15_PMCNTENCLR	0x000001FF44	32	woWrite-only	0x00000000	Provides the equivalent of the PMCNTENCLRx register, in the register map of a translation context bank. Disables any implemented event counter.
SMMU_CB15_PMCNTENSET	0x000001FF48	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter
SMMU_CB15_PMINTENCLR	0x000001FF4C	32	woWrite-only	0x00000000	Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter.
SMMU_CB15_PMOVSCLR	0x000001FF50	32	woWrite-only	0x00000000	Provides the equivalent of the PMOVSCLRx register, in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter.
SMMU_CB15_PMOVSSET	0x000001FF58	32	woWrite-only	0x00000000	Provides the equivalent of PMOVSSETx, in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters.
smmu_cb15_pmauthstatus	0x000001FFB8	32	roRead-only	0x00000080	Provides the equivalent of the PMAUTHSTATUS register, in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug permissions