CCI400 Module - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID

UG1087

Release Date

2024-03-13

Revision

1.10

CCI400 Module Description

Module Name	CCI400 Module
Modules of this Type	CCI_GPV
Base Addresses	0x00FD6E0000 (CCI_GPV)
Description	Cache Coherent Interconnect GPV

CCI400 Module Register Summary

Register Name	Offset Address	Width	Type	Reset Value	Description
Control_Override_Register	0x0000000000	32	rwNormal read/write	0x00000000	Control_Override_Register
Speculation_Control_Register	0x0000000004	32	rwNormal read/write	0x00000000	Speculation_Control_Register
Secure_Access_Register	0x0000000008	32	rwNormal read/write	0x00000000	Secure_Access_Register
Status_Register	0x000000000C	32	roRead-only	0x00000000	Status_Register
Imprecise_Error_Register	0x0000000010	32	wtcReadable, write a 1 to clear	0x00000000	Imprecise_Error_Register
Performance_Monitor_Control_Register	0x0000000100	32	mixedMixed types. See bit-field details.	0x00002000	Performance_Monitor_Control_Register
Snoop_Control_Register_S0	0x0000001000	32	mixedMixed types. See bit-field details.	0x80000000	Snoop_Control_Register_S0
Shareable_Override_Register_S0	0x0000001004	32	rwNormal read/write	0x00000000	Shareable_Override_Register_S0
Read_Qos_Override_Register_S0	0x0000001100	32	mixedMixed types. See bit-field details.	0x00000000	Read_Qos_Override_Register_S0
Write_Qos_Override_Register_S0	0x0000001104	32	mixedMixed types. See bit-field details.	0x00000000	Write_Qos_Override_Register_S0
Qos_Control_Register_S0	0x000000110C	32	mixedMixed types. See bit-field details.	0x00000000	Qos_Control_Register_S0
Max_OT_Register_S0	0x0000001110	32	rwNormal read/write	0x00000000	Max_OT_Register_S0
Target_Latency_Register_S0	0x0000001130	32	rwNormal read/write	0x00000000	Target_Latency_Register_S0
Latency_Regulation_Register_S0	0x0000001134	32	rwNormal read/write	0x00000000	Latency_Regulation_Register_S0
Qos_Range_Register_S0	0x0000001138	32	rwNormal read/write	0x00000000	Qos_Range_Register_S0
Snoop_Control_Register_S1	0x0000002000	32	roRead-only	0x00000000	Snoop_Control_Register_S1
Shareable_Override_Register_S1	0x0000002004	32	rwNormal read/write	0x00000000	Shareable_Override_Register_S1
Read_Qos_Override_Register_S1	0x0000002100	32	mixedMixed types. See bit-field details.	0x00000000	Read_Qos_Override_Register_S1
Write_Qos_Override_Register_S1	0x0000002104	32	mixedMixed types. See bit-field details.	0x00000000	Write_Qos_Override_Register_S1
Qos_Control_Register_S1	0x000000210C	32	mixedMixed types. See bit-field details.	0x00000000	Qos_Control_Register_S1
Max_OT_Register_S1	0x0000002110	32	rwNormal read/write	0x00000000	Max_OT_Register_S1
Target_Latency_Register_S1	0x0000002130	32	rwNormal read/write	0x00000000	Target_Latency_Register_S1
Latency_Regulation_Register_S1	0x0000002134	32	rwNormal read/write	0x00000000	Latency_Regulation_Register_S1
Qos_Range_Register_S1	0x0000002138	32	rwNormal read/write	0x00000000	Qos_Range_Register_S1
Snoop_Control_Register_S2	0x0000003000	32	roRead-only	0x00000000	Snoop_Control_Register_S2
Shareable_Override_Register_S2	0x0000003004	32	rwNormal read/write	0x00000000	Shareable_Override_Register_S2
Read_Qos_Override_Register_S2	0x0000003100	32	mixedMixed types. See bit-field details.	0x00000000	Read_Qos_Override_Register_S2
Write_Qos_Override_Register_S2	0x0000003104	32	mixedMixed types. See bit-field details.	0x00000000	Write_Qos_Override_Register_S2
Qos_Control_Register_S2	0x000000310C	32	mixedMixed types. See bit-field details.	0x00000000	Qos_Control_Register_S2
Max_OT_Register_S2	0x0000003110	32	rwNormal read/write	0x00000000	Max_OT_Register_S2
Target_Latency_Register_S2	0x0000003130	32	rwNormal read/write	0x00000000	Target_Latency_Register_S2
Latency_Regulation_Register_S2	0x0000003134	32	rwNormal read/write	0x00000000	Latency_Regulation_Register_S2
Qos_Range_Register_S2	0x0000003138	32	rwNormal read/write	0x00000000	Qos_Range_Register_S2
Snoop_Control_Register_S3	0x0000004000	32	mixedMixed types. See bit-field details.	0xC0000000	Snoop_Control_Register_S3
Read_Qos_Override_Register_S3	0x0000004100	32	mixedMixed types. See bit-field details.	0x00000000	Read_Qos_Override_Register_S3
Write_Qos_Override_Register_S3	0x0000004104	32	mixedMixed types. See bit-field details.	0x00000000	Write_Qos_Override_Register_S3
Qos_Control_Register_S3	0x000000410C	32	mixedMixed types. See bit-field details.	0x00000000	Qos_Control_Register_S3
Target_Latency_Register_S3	0x0000004130	32	rwNormal read/write	0x00000000	Target_Latency_Register_S3
Latency_Regulation_Register_S3	0x0000004134	32	rwNormal read/write	0x00000000	Latency_Regulation_Register_S3
Qos_Range_Register_S3	0x0000004138	32	rwNormal read/write	0x00000000	Qos_Range_Register_S3
Snoop_Control_Register_S4	0x0000005000	32	mixedMixed types. See bit-field details.	0xC0000000	Snoop_Control_Register_S4
Read_Qos_Override_Register_S4	0x0000005100	32	mixedMixed types. See bit-field details.	0x00000000	Read_Qos_Override_Register_S4
Write_Qos_Override_Register_S4	0x0000005104	32	mixedMixed types. See bit-field details.	0x00000000	Write_Qos_Override_Register_S4
Qos_Control_Register_S4	0x000000510C	32	mixedMixed types. See bit-field details.	0x00000000	Qos_Control_Register_S4
Target_Latency_Register_S4	0x0000005130	32	rwNormal read/write	0x00000000	Target_Latency_Register_S4
Latency_Regulation_Register_S4	0x0000005134	32	rwNormal read/write	0x00000000	Latency_Regulation_Register_S4
Qos_Range_Register_S4	0x0000005138	32	rwNormal read/write	0x00000000	Qos_Range_Register_S4
Cycle_Counter	0x0000009004	32	rwNormal read/write	0x00000000	Cycle_Counter
Cycle_Counter_Control	0x0000009008	32	rwNormal read/write	0x00000000	Cycle_Counter_Control
Cycle_Count_Overflow	0x000000900C	32	wtcReadable, write a 1 to clear	0x00000000	Cycle_Count_Overflow
ESR0	0x000000A000	32	rwNormal read/write	0x00000000	ESR0
Event_Counter0	0x000000A004	32	rwNormal read/write	0x00000000	Event_Counter0
Event_Counter0_Control	0x000000A008	32	rwNormal read/write	0x00000000	Event_Counter0_Control
Event_Counter0_Overflow	0x000000A00C	32	wtcReadable, write a 1 to clear	0x00000000	Event_Counter0_Overflow
ESR1	0x000000B000	32	rwNormal read/write	0x00000000	ESR1
Event_Counter1	0x000000B004	32	rwNormal read/write	0x00000000	Event_Counter1
Event_Counter1_Control	0x000000B008	32	rwNormal read/write	0x00000000	Event_Counter1_Control
Event_Counter1_Overflow	0x000000B00C	32	wtcReadable, write a 1 to clear	0x00000000	Event_Counter1_Overflow
ESR2	0x000000C000	32	rwNormal read/write	0x00000000	ESR2
Event_Counter2	0x000000C004	32	rwNormal read/write	0x00000000	Event_Counter2
Event_Counter2_Control	0x000000C008	32	rwNormal read/write	0x00000000	Event_Counter2_Control
Event_Counter2_Overflow	0x000000C00C	32	wtcReadable, write a 1 to clear	0x00000000	Event_Counter2_Overflow
ESR3	0x000000D000	32	rwNormal read/write	0x00000000	ESR3
Event_Counter3	0x000000D004	32	rwNormal read/write	0x00000000	Event_Counter3
Event_Counter3_Control	0x000000D008	32	rwNormal read/write	0x00000000	Event_Counter3_Control
Event_Counter3_Overflow	0x000000D00C	32	wtcReadable, write a 1 to clear	0x00000000	Event_Counter3_Overflow