AFIFM_RDCTRL (AFIFM) Register Description
| Register Name | AFIFM_RDCTRL |
|---|---|
| Offset Address | 0x0000000000 |
| Absolute Address |
0x00FD360000 (AFIFM0) 0x00FD370000 (AFIFM1) 0x00FD380000 (AFIFM2) 0x00FD390000 (AFIFM3) 0x00FD3A0000 (AFIFM4) 0x00FD3B0000 (AFIFM5) 0x00FF9B0000 (AFIFM6) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Read Channel Control Register |
Control fields for Read Channel operation Alternate register name: RDCTRL
AFIFM_RDCTRL (AFIFM) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:11 | razRead as zero | 0x0 | RESERVED. Return 0 when read. Writes ignored. |
| PAUSE | 3 | rwNormal read/write | 0x0 | Pause the issuing of new read commands to the PS-side. Existing outstanding commands will continue to be processed. |
| FABRIC_QOS_EN | 2 | rwNormal read/write | 0x0 | Enable control of QoS from the fabric 0: The QoS bits are derived from APB register, AFIFM_RDQoS.staticQoS 1: The QoS bits are dynamically driven from the fabric input, axds_arQoS[3:0] |
| FABRIC_WIDTH | 1:0 | rwNormal read/write | 0x0 | Configures the Read Channel Fabric interface width. 00: 128-bit 01: 64-bit 10: 32-bit 11: reserved |