Packet_Register (NAND) Register Description
| Register Name | Packet_Register |
|---|---|
| Offset Address | 0x0000000000 |
| Absolute Address | 0x00FF100000 (NAND) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000200 |
| Description | Packet Configuration. |
Packet_Register (NAND) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:24 | razRead as zero | 0x0 | reserved |
| Packet_count | 23:12 | rwNormal read/write | 0x0 | Packet count: 12'h001: 1 12'h002: 2 .. 12'h7FF: 2047 12'h800: 2048. Note: Change this value only when controller is not communicating with the memory device. |
| Reserved | 11 | razRead as zero | 0x0 | reserved |
| packet_size | 10:0 | rwNormal read/write | 0x200 | Size of the packet. Typical packet size is 11'h200bytes or 0x80 Dwords for BCH 4bit, 8bit, and 12bit Error correction. Typical packet size is 11'h400bytes or 0x100 Dwords for BCH 24bit Error correction. Note: Change this value only when controller is not communicating with the memory device. |