PIT1_COUNTER (PMU_IOMODULE) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

PIT1_COUNTER (PMU_IOMODULE) Register Description

Register NamePIT1_COUNTER
Offset Address0x0000000054
Absolute Address 0x00FFD40054 (PMU_IOMODULE)
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionPIT1 Counter Register

When reading this register the data obtained is a sample of the current counter value.

PIT1_COUNTER (PMU_IOMODULE) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
PIT1_COUNTER31:0roRead-only0x0PIT1 counter value at time of read