DATA_0 (GPIO) Register Description
| Register Name | DATA_0 |
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| Offset Address | 0x0000000040 |
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| Absolute Address |
0x00FF0A0040 (GPIO)
|
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| Width | 32 |
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| Type | mixedMixed types. See bit-field details. |
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| Reset Value | 0x00000000 |
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| Description | Output Data (GPIO Bank0, MIO) |
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This register controls the value being output when the GPIO signal is configured as an output. All 32bits of this register are written at one time. Reading from this register returns the previous value written to either DATA or MASK_DATA_{LSW,MSW}; it does not return the value on the device pin. NOTE: This register does not affect the enabling of the output driver. See the DIRM_0 and OEN_0 registers. This register controls the output values for bank0, which corresponds to MIO[25:0].
DATA_0 (GPIO) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|
| Reserved | 31:26 | razRead as zero | 0x0 | Not used, read back as zero |
| DATA_0 | 25:0 | rwNormal read/write | 0 | Output Data |