| Register Name | Offset Address | Width | Type | Reset Value | Description |
|---|
| MISC_CTRL | 0x0000000000 | 1 | rwNormal read/write | 0x00000000 | Controls for the register block. |
| ISR_0 | 0x0000000010 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Interrupt Status Register. This is a sticky register that holds the value of the interrupt until cleared by a value of 1. |
| IMR_0 | 0x0000000014 | 32 | mixedMixed types. See bit-field details. | 0x8000001F | Interrupt Mask Register. This is a read-only location and can be atomically altered by either the IDR or the IER. |
| IER_0 | 0x0000000018 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Interrupt Enable Register. A write of 1 to this location will unmask the interrupt |
| IDR_0 | 0x000000001C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Interrupt Disable Register. A write of 1 to this location will mask the interrupt |
| QREQN | 0x0000000040 | 32 | rwNormal read/write | 0x00007FFF | Low Power Signals for TBU |
| MISC | 0x0000000054 | 32 | rwNormal read/write | 0x00000000 | Miscellaneous signals |
| CONFIG_SIGNALS | 0x0000000058 | 32 | rwNormal read/write | 0x00000000 | Miscellaneous signals |