LOGCLR_ACK (PMU_LOCAL) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID: UG1087
Release Date: 2024-03-13
Revision: 1.10

LOGCLR_ACK (PMU_LOCAL) Register Description

Register Name	LOGCLR_ACK
Offset Address	0x0000000354
Absolute Address	0x00FFD60354 (PMU_LOCAL)
Width	32
Type	roRead-only
Reset Value	0x00000000
Description	This register provides the Acknowledge from the Logic Clear engines after they are run. (1 = Zeroization is Completed)

LOGCLR_ACK (PMU_LOCAL) Register Bit-Field Summary

Field Name	Bits	Type	Reset Value	Description
Reserved	31:18	roRead-only	0x0	reserved
FP	17	roRead-only	0x0	Logic Clear Ack for FP Domain besides A9s, GPU
LP	16	roRead-only	0x0	Logic Clear Ack for LP Domain besides PMU, RPU, and USBs
Reserved	15:14	roRead-only	0x0	reserved
USB1	13	roRead-only	0x0	Logic Clear Ack for USB1
USB0	12	roRead-only	0x0	Logic Clear Ack for USB0
Reserved	11	roRead-only	0x0	reserved
RPU	10	roRead-only	0x0	Logic Clear Ack for Dual_R5
Reserved	9:8	roRead-only	0x0	reserved
PP1	7	roRead-only	0x0	Logic Clear Ack for GPU PP1
PP0	6	roRead-only	0x0	Logic Clear Ack for GPU PP0
Reserved	5:4	roRead-only	0x0	reserved
ACPU3	3	roRead-only	0x0	Logic Clear Ack for ACPU3
ACPU2	2	roRead-only	0x0	Logic Clear Ack for ACPU2
ACPU1	1	roRead-only	0x0	Logic Clear Ack for ACPU1
ACPU0	0	roRead-only	0x0	Logic Clear Ack for ACPU0