PP1_PERF_CNT_1_ENABLE (GPU) Register Description
| Register Name | PP1_PERF_CNT_1_ENABLE |
|---|---|
| Offset Address | 0x000000B0A0 |
| Absolute Address | 0x00FD4BB0A0 (GPU) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Performance Counter 1 Enable Register |
PP1_PERF_CNT_1_ENABLE (GPU) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:2 | rwNormal read/write | 0x0 | Reserved, write as zero, read undefined. |
| PERF_CNT_1_LIM_EN | 1 | rwNormal read/write | 0x0 | When set to 1, the PERF_CNT_1_LIMIT Register becomes active. If the PERF_CNT_1_VALUE Register exceeds the Performance Counter 1 limit value, then an interrupt is asserted and the BUS_STOPPED mechanism stops the bus. The PERF_CNT_1_VALUE Register is reset to zero if you write to PERF_CNT_1_ENABLE while the counter is enabled, that is, the PERF_CNT_1_ENABLE bit is 1. |
| PERF_CNT_1_ENABLE | 0 | rwNormal read/write | 0x0 | When set to 1, the performance counter 1 is reset to zero and activated. The PERF_CNT_1_SRC Register selects the event to be counted during a frame. |