L0_TM_PLL_DIG_37 (SERDES) Register Description
| Register Name | L0_TM_PLL_DIG_37 |
|---|---|
| Offset Address | 0x0000002094 |
| Absolute Address | 0x00FD402094 (SERDES) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Register value is generated by Vivado PCW. |
L0_TM_PLL_DIG_37 (SERDES) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| TM_PLL_DIG_37_31_8_rsvd | 31:8 | roRead-only | 0x0 | Value generated by PCW. |
| tm_coarse_code_sat_value_lsb | 7:5 | rwNormal read/write | 0x0 | Value generated by PCW. |
| tm_enable_coarse_saturation | 4 | rwNormal read/write | 0x0 | Value generated by PCW. |
| w_spare_outputs | 3:2 | rwNormal read/write | 0x0 | Value generated by PCW. |
| tm_force_en_ip_div_bypass | 1 | rwNormal read/write | 0x0 | Value generated by PCW. |
| tm_en_ip_div_bypass | 0 | rwNormal read/write | 0x0 | Value generated by PCW. |