reg_autocmderrsts (SDIO) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

reg_autocmderrsts (SDIO) Register Description

Register Namereg_autocmderrsts
Offset Address0x000000003C
Absolute Address 0x00FF16003C (SD0)
0x00FF17003C (SD1)
Width16
TyperoRead-only
Reset Value0x00000000
DescriptionCMD12 response error of Auto CMD12 and CMD23.

reg_autocmderrsts (SDIO) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
autocmderrsts_nexterror 7roRead-only0x0Setting this bit to 1 means CMD_wo_DAT is not executed due to an Auto CMD12 error (D04- D01) in this register. This bit is set to 0 when Auto CMD Error is generated by Auto CMD23.
0 No Error
1 Not Issued
autocmderrsts_indexerror 4roRead-only0x0Occurs if the Command Index error occurs in response to a command.
0 No Error,
1 Error.
autocmderrsts_endbiterror 3roRead-only0x0Occurs when detecting that the end bit of command response is 0.
0 No Error,
1 End Bit Error Generated
autocmderrsts_crcerror 2roRead-only0x0Occurs when detecting a CRC error in the command response.
0 No error
1 CRC Error Generated
autocmderrsts_timeouterror 1roRead-only0x0Occurs if the no response is returned within 64 SDCLK cycles from the end bit of the command.If this bit is set to 1, the other error status bits (D04 - D02) are meaningless.
0 No error
1 Timeout
autocmderrsts_notexecerror 0roRead-only0x0If memory multiple block data transfer is not started due to command error, this bit is not set because it is not necessary to issue Auto CMD12. Setting this bit to 1 means the HC cannot issue Auto CMD12 to stop memory multiple block transfer due to some error. If this bit is set to 1, other error status bits (D04 - D01) are meaningless. This bit is set to 0 when Auto CMD Error is generated by Auto CMD23
0 Executed, 1 Not Executed