SMMU_CB12_PMCEID (SMMU500) Register

Zynq UltraScale+ Devices Register Reference (UG1087)
Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

SMMU_CB12_PMCEID (SMMU500) Register Description

Register NameSMMU_CB12_PMCEID
Offset Address0x000001CF20
Absolute Address 0x00FD81CF20 (SMMU_GPV)
Width32
TyperoRead-only
Reset Value0x00030303
DescriptionProvide the equivalent of the SMMU performance monitoring register map PMCEID0 register, in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation.

SMMU_CB12_PMCEID (SMMU500) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Event0x1217roRead-only0x1Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
Event0x1116roRead-only0x1Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
Event0x1015roRead-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
Event0x0A 9roRead-only0x1Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
Event0x09 8roRead-only0x1Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
Event0x08 7roRead-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
Event0x01 1roRead-only0x1Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
Event0x00 0roRead-only0x1Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details