SMMU_CB2_TLBIASID (SMMU500) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

SMMU_CB2_TLBIASID (SMMU500) Register Description

Register NameSMMU_CB2_TLBIASID
Offset Address0x0000012610
Absolute Address 0x00FD812610 (SMMU_GPV)
Width32
TypewoWrite-only
Reset Value0x00000000
DescriptionInvalidates all of the unlocked TLB entries that match the ASID provided as an argument

SMMU_CB2_TLBIASID (SMMU500) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
ASID15:0woWrite-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details