Flow_delay (UART) Register Description
| Register Name | Flow_delay |
|---|---|
| Offset Address | 0x0000000038 |
| Absolute Address |
0x00FF000038 (UART0) 0x00FF010038 (UART1) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Flow Control Delay Register |
The Flow Control Delay register is only used if automatic flow control mode is enabled in the FCM field in the Modem Control register. When automatic flow control mode is enabled, this register specifies the receiver FIFO level at which the EMIOUARTxRTSN output is de-asserted. The EMIOUARTxRTSN output is only asserted again once the fill level drops to below four less than FDEL.
Flow_delay (UART) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:6 | roRead-only | 0x0 | Reserved, read as zero, ignored on write. |
| FDEL | 5:0 | rwNormal read/write | 0x0 | RxFIFO trigger level for Ready To Send (RTS) output signal (EMIOUARTxRTSN) de-assertion: 0 - 3: Flow delay triggering is disabled, since minimum 4 word hysteresis cannot be satisfied. 4 to 65535: EMIOUARTxRTSN is driven high when Rx FIFO fill level equals FDEL |