SMMU_CB0_PMCFGR (SMMU500) Register - SMMU_CB0_PMCFGR (SMMU500) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID: UG1087
Release Date: 2025-06-20
Revision: 1.11

SMMU_CB0_PMCFGR (SMMU500) Register Description

Register Name	SMMU_CB0_PMCFGR
Offset Address	0x0000010F00
Absolute Address	0x00FD810F00 (SMMU_GPV)
Width	32
Type	roRead-only
Reset Value	0x00011F03
Description	Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data.

SMMU_CB0_PMCFGR (SMMU500) Register Bit-Field Summary

Field Name	Bits	Type	Reset Value	Description
NCG	31:24	roRead-only	0x0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
UEN	19	roRead-only	0x0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
EX	16	roRead-only	0x1	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
CCD	15	roRead-only	0x0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
CC	14	roRead-only	0x0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
SIZE	13:8	roRead-only	0x1F	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
N	7:0	roRead-only	0x3	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details