L3_TM_CDR5 (SERDES) Register Description
| Register Name | L3_TM_CDR5 |
|---|---|
| Offset Address | 0x000000DC14 |
| Absolute Address | 0x00FD40DC14 (SERDES) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Register value is generated by Vivado PCW. |
L3_TM_CDR5 (SERDES) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| TM_CDR5_31_8_rsvd | 31:8 | roRead-only | 0x0 | Value generated by PCW. |
| fphl_fsm_acc_cycles | 7:5 | rwNormal read/write | 0x0 | Value generated by PCW. |
| ffl_ph0_int_gain | 4:0 | rwNormal read/write | 0x0 | Value generated by PCW. |