ZDMA_ERR_CTRL (ZDMA) Register Description
| Register Name | ZDMA_ERR_CTRL |
|---|---|
| Offset Address | 0x0000000000 |
| Absolute Address |
0x00FFA80000 (ADMA_CH0) 0x00FFA90000 (ADMA_CH1) 0x00FFAA0000 (ADMA_CH2) 0x00FFAB0000 (ADMA_CH3) 0x00FFAC0000 (ADMA_CH4) 0x00FFAD0000 (ADMA_CH5) 0x00FFAE0000 (ADMA_CH6) 0x00FFAF0000 (ADMA_CH7) 0x00FD500000 (GDMA_CH0) 0x00FD510000 (GDMA_CH1) 0x00FD520000 (GDMA_CH2) 0x00FD530000 (GDMA_CH3) 0x00FD540000 (GDMA_CH4) 0x00FD550000 (GDMA_CH5) 0x00FD560000 (GDMA_CH6) 0x00FD570000 (GDMA_CH7) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000001 |
| Description | Enable/Disable a error response |
By default, invalid address requests are ignored. However, a maskable interrupt exists. By enabling this slverr_enable invalid address requests cause a slverr to occur.
ZDMA_ERR_CTRL (ZDMA) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:1 | razRead as zero | 0x0 | Reserved for future use |
| APB_ERR_RES | 0 | rwNormal read/write | 0x1 | When an APB (register) access occurs to an unimplemented space (there is no register at that location), the resulting pslverr will be: 0: pslverr = 0 1: pslverr = 1 There is also a maskable interrupt , "INV_APB_INT" that could be asserted, independent of what option is selected here. |