MIO_PIN_76 (IOU_SLCR) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

MIO_PIN_76 (IOU_SLCR) Register Description

Register NameMIO_PIN_76
Offset Address0x0000000130
Absolute Address 0x00FF180130 (IOU_SLCR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionMIO Device Pin 76 Multiplexer Controls.

MIO_PIN_76 (IOU_SLCR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:8rwNormal read/write0x0reserved
L3_SEL 7:5rwNormal read/write0x0Level 3 Mux Select:
0: GPIO [76] input/output bank 2.
1: CAN1 TX output.
2: I2C1 SCL input/output clock.
3: mdio0 output gem0_mdc- (MDIO Clock)
4: mdio1 output gem1_mdc- (MDIO Clock)
5: mdio2 output gem2_mdc- (MDIO Clock)
6: mdio3 output gem3_mdc- (MDIO Clock)
7: reserved
L2_SEL 4:3rwNormal read/write0x0Level 2 Mux Select:
0: Level 3 Mux output
1: SDIO0 Write Protect input.
2: SDIO1 Clock output.
L1_SEL 2rwNormal read/write0x0Level 1 Mux Select:
0: Level 2 Mux output
1: reserved
L0_SEL 1rwNormal read/write0x0Level 0 Mux Select:
0: Level 1 Mux output
1: reserved
Reserved 0rwNormal read/write0x0reserved