PLLCR4 (DDR_PHY) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

PLLCR4 (DDR_PHY) Register Description

Register NamePLLCR4
Offset Address0x0000000078
Absolute Address 0x00FD080078 (DDR_PHY)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionPLL Control Register 4 (Type B PLL Only)

PLLCR4 (DDR_PHY) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
PLLCTRL_95_6431:0rwNormal read/write0x0Connects to bits [95:64] of the PLL general control bus PLL_CTRL