DMACTLR (STM) Register Description
| Register Name | DMACTLR |
|---|---|
| Offset Address | 0x0000000C10 |
| Absolute Address | 0x00FE9C0C10 (CORESIGHT_SOC_STM) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Controls the DMA transfer request mechanism. |
DMACTLR (STM) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| SENS | 3:2 | rwNormal read/write | 0x0 | Determines the sensitivity of the DMA request to the current buffer level in the STM: 0: Empty 1: 25% 2: 50% 3: 75% |