SMMU_CB8_FAR_low (SMMU500) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

SMMU_CB8_FAR_low (SMMU500) Register Description

Register NameSMMU_CB8_FAR_low
Offset Address0x0000018060
Absolute Address 0x00FD818060 (SMMU_GPV)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionHolds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception.

SMMU_CB8_FAR_low (SMMU500) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
bits31:0rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details