GPI1_ENABLE (PMU_LOCAL) Register Description
| Register Name | GPI1_ENABLE |
|---|
| Offset Address | 0x0000000224 |
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| Absolute Address |
0x00FFD60224 (PMU_LOCAL)
|
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| Width | 32 |
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| Type | mixedMixed types. See bit-field details. |
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| Reset Value | 0x00000000 |
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| Description | Enable Events on PMU GPI1 Input Register. |
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Enable the propagation of events to the GPI1 interface of the PMU. 0: disable. 1: enable. GPI1 interrupt will be generated by all events that are enabled in this register.
GPI1_ENABLE (PMU_LOCAL) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|
| APB_AIB_Error | 31 | rwNormal read/write | 0x0 | APB AIB isolation access error. A powered-down block is accessed through APB. |
| AXI_AIB_Error | 30 | rwNormal read/write | 0x0 | AXI AIB isolation access error. A powered-down block is accessed through AXI. |
| Error_Reg2_Int | 29 | rwNormal read/write | 0x0 | PMU signal to show an unmasked error in ERROR_STATUS_2 register. |
| Error_Reg1_Int | 28 | rwNormal read/write | 0x0 | PMU signal to show an unmasked error in ERROR_STATUS_1 register. |
| Reserved | 27:24 | roRead-only | 0x0 | reserved |
| Dbg_ACPU3_Pwrup_Req | 23 | rwNormal read/write | 0x0 | Debug Powerup request for APU core 3. |
| Dbg_ACPU2_Pwrup_Req | 22 | rwNormal read/write | 0x0 | Debug Powerup request for APU core 2. |
| Dbg_ACPU1_Pwrup_Req | 21 | rwNormal read/write | 0x0 | Debug Powerup request for APU core 1. |
| Dbg_ACPU0_Pwrup_Req | 20 | rwNormal read/write | 0x0 | Debug Powerup request for APU core 0. |
| Reserved | 19:17 | roRead-only | 0x0 | reserved |
| FPD_Wake_GIC_Prox | 16 | rwNormal read/write | 0x0 | FPD wake-up directed by the GIC Proxy interrupt controller. |
| MIO_Wake | 15:10 | rwNormal read/write | 0x0 | General-Purpose wake-up signals from MIO. |
| DAP_RPU_Wake | 9 | rwNormal read/write | 0x0 | DAP controller RPU wake-up request. |
| DAP_FP_Wake | 8 | rwNormal read/write | 0x0 | DAP controller FPD wake-up request. |
| USB1_Wake | 7 | rwNormal read/write | 0x0 | USB controller 1 wake |
| USB0_Wake | 6 | rwNormal read/write | 0x0 | USB controller 0 wake. |
| R5_1_Wake | 5 | rwNormal read/write | 0x0 | RPU core 1 wake from LPD GIC interrupt controller. |
| R5_0_Wake | 4 | rwNormal read/write | 0x0 | RPU core 0 wake from LPD GIC interrupt controller. |
| ACPU3_Wake | 3 | rwNormal read/write | 0x0 | APU core 3 wake from FPD GIC interrupt controller. |
| ACPU2_Wake | 2 | rwNormal read/write | 0x0 | APU core 2 wake from FPD GIC interrupt controller. |
| ACPU1_Wake | 1 | rwNormal read/write | 0x0 | APU core 1 wake from FPD GIC interrupt controller. |
| ACPU0_Wake | 0 | rwNormal read/write | 0x0 | APU core 0 wake from FPD GIC interrupt controller. |