GPI2_ENABLE (PMU_LOCAL) Register Description
| Register Name | GPI2_ENABLE |
|---|
| Offset Address | 0x0000000228 |
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| Absolute Address |
0x00FFD60228 (PMU_LOCAL)
|
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| Width | 32 |
|---|
| Type | mixedMixed types. See bit-field details. |
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| Reset Value | 0x00000000 |
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| Description | Enable Events on PMU GPI2 Input Register. |
|---|
Enable the propagation of events to the GPI2 interface of the PMU. GPI2 interrupt will be generated by all events that are enabled in this register.
GPI2_ENABLE (PMU_LOCAL) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|
| VCC_PSINTFP_Alarm | 31 | rwNormal read/write | 0x0 | Alarm when VCC_PSINTFP voltage is removed. |
| VCC_PSINT_Alarm | 30 | rwNormal read/write | 0x0 | Alarm when VCC_PSINT voltage is removed. |
| VCC_PSAUX_Alarm | 29 | rwNormal read/write | 0x0 | Alarm when VCC_PSAUX voltage is removed. |
| Reserved | 28:24 | roRead-only | 0x0 | reserved |
| Dbg_ACPU3_Rst_Req | 23 | rwNormal read/write | 0x0 | Warm Reset Request for APU core 3 from the APU debug logic. |
| Dbg_ACPU2_Rst_Req | 22 | rwNormal read/write | 0x0 | Warm Reset Request for APU core 2 from the APU debug logic. |
| Dbg_ACPU1_Rst_Req | 21 | rwNormal read/write | 0x0 | Warm Reset Request for APU core 1 from the APU debug logic. |
| Dbg_ACPU0_Rst_Req | 20 | rwNormal read/write | 0x0 | Warm Reset Request for APU core 0 from the APU debug logic. |
| CP_ACPU3_Rst_Req | 19 | rwNormal read/write | 0x0 | Warm Reset request for APU core 3 from the APU CP. |
| CP_ACPU2_Rst_Req | 18 | rwNormal read/write | 0x0 | Warm Reset request for APU core 2 from the APU CP. |
| CP_ACPU1_Rst_Req | 17 | rwNormal read/write | 0x0 | Warm Reset request for APU core 1 from the APU CP. |
| CP_ACPU0_Rst_Req | 16 | rwNormal read/write | 0x0 | Warm Reset request for APU core 0 from the APU CP. |
| Reserved | 15:10 | roRead-only | 0x0 | reserved |
| Dbg_RPU1_Rst_Req | 9 | rwNormal read/write | 0x0 | Warm Reset request for RPU core 1 from the RPU debug logic. |
| Dbg_RPU0_Rst_Req | 8 | rwNormal read/write | 0x0 | Warm Reset request for RPU core 0 from the RPU debug logic. |
| Reserved | 7 | roRead-only | 0x0 | reserved |
| FP_LP_Pwrdwn_Ack | 6 | rwNormal read/write | 0x0 | Power-down acknowledge from FPD-LPD bridge. |
| R5_1_Pwrdwn_Req | 5 | rwNormal read/write | 0x0 | Power-down request from RPU core 1. |
| R5_0_Pwrdwn_Req | 4 | rwNormal read/write | 0x0 | Power-down request from RPU core 0. |
| ACPU3_Pwrdwn_Req | 3 | rwNormal read/write | 0x0 | Power-down request from APU core 3. |
| ACPU2_Pwrdwn_Req | 2 | rwNormal read/write | 0x0 | Power-down request from APU core 2. |
| ACPU1_Pwrdwn_Req | 1 | rwNormal read/write | 0x0 | Power-down request from APU core 1. |
| ACPU0_Pwrdwn_Req | 0 | rwNormal read/write | 0x0 | Power-down request from APU core 0. |