ECCUADDR1 (DDRC) Register Description
| Register Name | ECCUADDR1 |
|---|---|
| Offset Address | 0x00000000A8 |
| Absolute Address | 0x00FD0700A8 (DDRC) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x00000000 |
| Description | ECC Uncorrected Error Address Register 1 |
ECCUADDR1 (DDRC) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| ecc_uncorr_bg | 25:24 | roRead-only | 0x0 | Bank Group number of a read resulting in an uncorrected ECC error |
| ecc_uncorr_bank | 18:16 | roRead-only | 0x0 | Bank number of a read resulting in an uncorrected ECC error |
| ecc_uncorr_col | 11:0 | roRead-only | 0x0 | Block number of a read resulting in an uncorrected ECC error (lowest bit not assigned here) |