CAN_MIO_CTRL (IOU_SLCR) Register Description
| Register Name | CAN_MIO_CTRL |
|---|---|
| Offset Address | 0x0000000304 |
| Absolute Address | 0x00FF180304 (IOU_SLCR) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | CAN MIO Control |
CAN_MIO_CTRL (IOU_SLCR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:24 | razRead as zero | 0x0 | Reserved. Writes are ignored, read data is zero. |
| CAN1_RXIN_REG | 23 | rwNormal read/write | 0x0 | CAN1 Reference Clock selection: 1: Clock CAN PHY input on rising edge of clock. 0: Clock CAN PHY input on falling edge of clock. |
| CAN1_REF_SEL | 22 | rwNormal read/write | 0x0 | CAN1 Reference Clock selection: 0: From internal PLL. 1: From MIO based on the [CAN1_MUX] bit field. |
| CAN1_MUX | 21:15 | rwNormal read/write | 0x0 | CAN1 clock selection when using MIO as source. 0: select MIO[0] 1: select MIO[1] .. 4C: select MIO[76] 4D: select MIO[77] Others are reserved. |
| Reserved | 14:9 | rwNormal read/write | 0x0 | Reserved. Writes are ignored, read data is zero. |
| CAN0_RXIN_REG | 8 | rwNormal read/write | 0x0 | CAN0 Reference Clock selection: 1: Clock CAN PHY input on rising edge of clock. 0: Clock CAN PHY input on falling edge of clock. |
| CAN0_REF_SEL | 7 | rwNormal read/write | 0x0 | CAN0 Reference Clock selection: 0: From internal PLL 1: From MIO based on the [CAN0_MUX] bit field. |
| CAN0_MUX | 6:0 | rwNormal read/write | 0x0 | CAN0 clock selection when using MIO as source. 0: select MIO[0] 1: select MIO[1] .. 4C: select MIO[76] 4D: select MIO[77] Others are reserved. |