MIO_MST_TRI2 (IOU_SLCR) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID: UG1087
Release Date: 2024-03-13
Revision: 1.10

MIO_MST_TRI2 (IOU_SLCR) Register Description

Register Name	MIO_MST_TRI2
Offset Address	0x000000020C
Absolute Address	0x00FF18020C (IOU_SLCR)
Width	32
Type	mixedMixed types. See bit-field details.
Reset Value	0x00003FFF
Description	MIO pin Tri-state Enables, 77:64

MIO_MST_TRI2 (IOU_SLCR) Register Bit-Field Summary

Field Name	Bits	Type	Reset Value	Description
Reserved	31:14	razRead as zero	0x0	reserved
PIN_77_TRI	13	rwNormal read/write	0x1	Master Tri-state Enable for pin 77, active high
PIN_76_TRI	12	rwNormal read/write	0x1	Master Tri-state Enable for pin 76, active high
PIN_75_TRI	11	rwNormal read/write	0x1	Master Tri-state Enable for pin 75, active high
PIN_74_TRI	10	rwNormal read/write	0x1	Master Tri-state Enable for pin 74, active high
PIN_73_TRI	9	rwNormal read/write	0x1	Master Tri-state Enable for pin 73, active high
PIN_72_TRI	8	rwNormal read/write	0x1	Master Tri-state Enable for pin 72, active high
PIN_71_TRI	7	rwNormal read/write	0x1	Master Tri-state Enable for pin 71, active high
PIN_70_TRI	6	rwNormal read/write	0x1	Master Tri-state Enable for pin 70, active high
PIN_69_TRI	5	rwNormal read/write	0x1	Master Tri-state Enable for pin 69, active high
PIN_68_TRI	4	rwNormal read/write	0x1	Master Tri-state Enable for pin 68, active high
PIN_67_TRI	3	rwNormal read/write	0x1	Master Tri-state Enable for pin 67, active high
PIN_66_TRI	2	rwNormal read/write	0x1	Master Tri-state Enable for pin 66, active high
PIN_65_TRI	1	rwNormal read/write	0x1	Master Tri-state Enable for pin 65, active high
PIN_64_TRI	0	rwNormal read/write	0x1	Master Tri-state Enable for pin 64, active high