VCU_IMR (VCU_SLCR) Register Description
| Register Name | VCU_IMR |
|---|---|
| Offset Address | 0x0000000074 |
| Absolute Address | 0x00A0040074 (VCU_SLCR) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x000FFFFF |
| Description | Interrupt Mask Register for intrN. This is a read-only location and can be atomically altered by either the IDR or the IER. |
VCU_IMR (VCU_SLCR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| apm3_fifo3_ovfl | 19 | roRead-only | 0x1 | Overflow occured on 2nd read latency measurement FIFO. This is for 2nd Decoder AXI4 Bus. |
| apm3_fifo2_ovfl | 18 | roRead-only | 0x1 | Overflow occured on 1st read latency measurement FIFO. This is for 2nd Decoder AXI4 Bus. |
| apm3_fifo1_ovfl | 17 | roRead-only | 0x1 | Overflow occured on 2nd write latency measurement FIFO. This is for 2nd Decoder AXI4 Bus. |
| apm3_fifo0_ovfl | 16 | roRead-only | 0x1 | Overflow occured on 1st write latency measurement FIFO. This is for 2nd Decoder AXI4 Bus. |
| apm3_result_valid | 15 | roRead-only | 0x1 | Timing window completion interrupt. This indicates that performance measurement results are available for read. This is for 2nd Decoder AXI4 Bus. |
| apm2_fifo3_ovfl | 14 | roRead-only | 0x1 | Overflow occured on 2nd read latency measurement FIFO. This is for 1st Decoder AXI4 Bus. |
| apm2_fifo2_ovfl | 13 | roRead-only | 0x1 | Overflow occured on 1st read latency measurement FIFO. This is for 1st Decoder AXI4 Bus. |
| apm2_fifo1_ovfl | 12 | roRead-only | 0x1 | Overflow occured on 2nd write latency measurement FIFO. This is for 1st Decoder AXI4 Bus. |
| apm2_fifo0_ovfl | 11 | roRead-only | 0x1 | Overflow occured on 1st write latency measurement FIFO. This is for 1st Decoder AXI4 Bus. |
| apm2_result_valid | 10 | roRead-only | 0x1 | Timing window completion interrupt. This indicates that performance measurement results are available for read. This is for 1st Decoder AXI4 Bus. |
| apm1_fifo3_ovfl | 9 | roRead-only | 0x1 | Overflow occured on 2nd read latency measurement FIFO. This for is 2nd Encoder AXI4 Bus. |
| apm1_fifo2_ovfl | 8 | roRead-only | 0x1 | Overflow occured on 1st read latency measurement FIFO. This is for 2nd Encoder AXI4 Bus. |
| apm1_fifo1_ovfl | 7 | roRead-only | 0x1 | Overflow occured on 2nd write latency measurement FIFO. This is for 2nd Encoder AXI4 Bus. |
| apm1_fifo0_ovfl | 6 | roRead-only | 0x1 | Overflow occured on 1st write latency measurement FIFO. This is for 2nd Encoder AXI4 Bus. |
| apm1_result_valid | 5 | roRead-only | 0x1 | Timing window completion interrupt. This indicates that performance measurement results are available for read. This is for 2nd Encoder AXI4 Bus. |
| apm0_fifo3_ovfl | 4 | roRead-only | 0x1 | Overflow occured on 2nd read latency measurement FIFO. This is for 1st Encoder AXI4 Bus. |
| apm0_fifo2_ovfl | 3 | roRead-only | 0x1 | Overflow occured on 1st read latency measurement FIFO. This is for 1st Encoder AXI4 Bus. |
| apm0_fifo1_ovfl | 2 | roRead-only | 0x1 | Overflow occured on 2nd write latency measurement FIFO. This is for 1st Encoder AXI4 Bus. |
| apm0_fifo0_ovfl | 1 | roRead-only | 0x1 | Overflow occured on 1st write latency measurement FIFO. This is for 1st Encoder AXI4 Bus. |
| apm0_result_valid | 0 | roRead-only | 0x1 | Timing window completion interrupt. This indicates that performance measurement results are available for read. This is 1st Encoder AXI4 Bus. |