RFSHTMG (DDRC) Register Description
| Register Name | RFSHTMG |
|---|---|
| Offset Address | 0x0000000064 |
| Absolute Address | 0x00FD070064 (DDRC) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x0062008C |
| Description | Refresh Timing Register |
All register fields are dynamic - refresh related, unless described otherwise in the register field description. Refresh related dynamic registers can be written at any time during operation, but to update them the following must be done: * Change the refresh associated register as desired. * After the changed register is known stable, toggle the RFSHCTL3.refresh_update_level signal.
RFSHTMG (DDRC) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| t_rfc_nom_x32 | 27:16 | rwNormal read/write | 0x62 | tREFI: Average time interval between refreshes per rank (Specification: 7.8us for DDR3 and DDR4. See JEDEC specification for LPDDR3 and LPDDR4). For LPDDR3/LPDDR4: - if using all-bank refreshes (RFSHCTL0.per_bank_refresh = 0), this register should be set to tREFIab - if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this register should be set to tREFIpb Program this to (tREFI/2), no rounding up. In DDR4 mode, tREFI value is different depending on the refresh mode. The user should program the appropriate value from the spec based on the value programmed in the refresh mode register. Note that RFSHTMG.t_rfc_nom_x32 * 32 must be greater than RFSHTMG.t_rfc_min, and RFSHTMG.t_rfc_nom_x32 must be greater than 0x1. Unit: Multiples of 32 clocks. |
| lpddr3_trefbw_en | 15 | rwNormal read/write | 0x0 | Used only when LPDDR3 memory type is connected. Should only be changed when DDRC is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not: - 0 - tREFBW parameter not used - 1 - tREFBW parameter used Programming Mode: Static |
| t_rfc_min | 9:0 | rwNormal read/write | 0x8C | tRFC (min): Minimum time from refresh to refresh or activate. t_rfc_min should be set to RoundUp(RoundUp(tRFCmin/tCK)/2). In LPDDR3/LPDDR4 mode: - if using all-bank refreshes, the tRFCmin value in the above equations is equal to tRFCab - if using per-bank refreshes, the tRFCmin value in the above equations is equal to tRFCpb In DDR4 mode, the tRFCmin value in the above equations is different depending on the refresh mode (fixed 1X,2X,4X) and the device density. The user should program the appropriate value from the spec based on the refresh_mode and the device density that is used. Unit: Clocks. |