L0_L3_REF_CLK_SEL (SERDES) Register Description
| Register Name | L0_L3_REF_CLK_SEL |
|---|---|
| Offset Address | 0x000000286C |
| Absolute Address | 0x00FD40286C (SERDES) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000080 |
| Description | Register value is generated by Vivado PCW. |
L0_L3_REF_CLK_SEL (SERDES) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| L3_REF_CLK_SEL_31_8_rsvd | 31:8 | roRead-only | 0x0 | Value generated by PCW. |
| L3_ref_clk_lcl_sel | 7 | rwNormal read/write | 0x1 | Value generated by PCW. |
| L3_REFCLK_SEL_6_rsvd | 6 | roRead-only | 0x0 | Value generated by PCW. |
| L3_REFCLK_SEL_5_rsvd | 5 | roRead-only | 0x0 | Value generated by PCW. |
| L3_ref_clk_sel_4 | 4 | rwNormal read/write | 0x0 | Value generated by PCW. |
| L3_ref_clk_sel_3 | 3 | rwNormal read/write | 0x0 | Value generated by PCW. |
| L3_ref_clk_sel_2 | 2 | rwNormal read/write | 0x0 | Value generated by PCW. |
| L3_ref_clk_sel_1 | 1 | rwNormal read/write | 0x0 | Value generated by PCW. |
| L3_ref_clk_sel_0 | 0 | rwNormal read/write | 0x0 | Value generated by PCW. |