QSPIDMA_DST_I_STS (QSPI) Register Description
| Register Name | QSPIDMA_DST_I_STS |
|---|---|
| Offset Address | 0x0000000814 |
| Absolute Address | 0x00FF0F0814 (QSPI) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | DST DMA Interrupt Status |
Pre-mask interrupt status. Read: 0: no interrupt event. 1: interrupt event. Write: 0: no effect. 1: clear status bit.
QSPIDMA_DST_I_STS (QSPI) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:8 | razRead as zero | 0x0 | reserved |
| FIFO_OVERFLOW | 7 | wtcReadable, write a 1 to clear | 0x0 | DST FIFO Overflow. No backpressure mechanism exists on the stream interface in this direction. If the FIFO is full and 1 more data beat is produced by the stream interface, this bit will be set and the data beat will be discarded. If [PAUSE_STRM] is asserted and the stream interface produces a beat of data, the beat will be discarded and [FIFO_OVERFLOW] will be set. |
| INVALID_APB | 6 | wtcReadable, write a 1 to clear | 0x0 | APB Address Decode Error. The access request did not reach a register. |
| THRESH_HIT | 5 | wtcReadable, write a 1 to clear | 0x0 | DST FIFO Reached Watermark Value. The watermark value is set via the [FIFO_THRESH] bitfield. |
| TIMEOUT_MEM | 4 | wtcReadable, write a 1 to clear | 0x0 | Timeout Counter #1 Expired. DST DMA sees backpressure on AXI write data interface. Refer to [TIMEOUT_VAL] description for exact timeout duration and conditions. |
| TIMEOUT_STRM | 3 | wtcReadable, write a 1 to clear | 0x0 | Timeout Counter #2 Expired. DST DMA sees delay on SSS DST interface. Refer to [TIMEOUT_VAL] description for exact timeout duration and conditions. |
| AXI_BRESP_ERR | 2 | wtcReadable, write a 1 to clear | 0x0 | AXI Memory Write Error. BRESP=DECERR/SLVERR. |
| DONE | 1 | wtcReadable, write a 1 to clear | 0x0 | DMA Completed Write Command. The last associated AXI memory write command has been issued and processed (SIZE=0), all data has been sent (DST FIFO is empty) and all outstanding BRESPs have been received. |
| Reserved | 0 | razRead as zero | 0x0 | reserved |