int_q1_enable (GEM) Register Description
| Register Name | int_q1_enable |
|---|---|
| Offset Address | 0x0000000600 |
| Absolute Address |
0x00FF0B0600 (GEM0) 0x00FF0C0600 (GEM1) 0x00FF0D0600 (GEM2) 0x00FF0E0600 (GEM3) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | At reset all interrupts are disabled. Writing a one to the relevant bit location enables the required interrupt. This register is write only and when read will return zero. |
int_q1_enable (GEM) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:12 | roRead-only | 0x0 | Reserved, read as 0, ignored on write. |
| enable_resp_not_ok_interrupt | 11 | woWrite-only | 0x0 | Enable bresp/hresp not OK interrupt |
| enable_receive_overrun_interrupt | 10 | woWrite-only | 0x0 | Enable Receive overrun interrupt |
| Reserved | 9:8 | roRead-only | 0x0 | Reserved, read as 0, ignored on write. |
| enable_transmit_complete_interrupt | 7 | woWrite-only | 0x0 | Enable Transmit complete interrupt |
| enable_transmit_frame_corruption_due_to_amba_error_interrupt | 6 | woWrite-only | 0x0 | Enable Transmit frame corruption due to AMBA (AHB/AXI) error interrupt |
| enable_retry_limit_exceeded_or_late_collision_interrupt | 5 | woWrite-only | 0x0 | Enable Retry limit exceeded or late collision interrupt |
| Reserved | 4:3 | roRead-only | 0x0 | Reserved, read as 0, ignored on write. |
| enable_rx_used_bit_read_interrupt | 2 | woWrite-only | 0x0 | Enable RX used bit read interrupt |
| enable_receive_complete_interrupt | 1 | woWrite-only | 0x0 | Enable Receive complete interrupt |
| Reserved | 0 | roRead-only | 0x0 | Reserved, read as 0, ignored on write. |