CLKMON_ENABLE (CRL_APB) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

CLKMON_ENABLE (CRL_APB) Register Description

Register NameCLKMON_ENABLE
Offset Address0x0000000148
Absolute Address 0x00FF5E0148 (CRL_APB)
Width16
TypewoWrite-only
Reset Value0x00000000
DescriptionClock Monitor Interrupt Enable.

A write of to this location will unmask the interrupt: CLKMON_MASK set = 0.

CLKMON_ENABLE (CRL_APB) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
cnta7_over_err15woWrite-only0x0Enable for clk_check
mon7_err14woWrite-only0x0Enable for clk_check
cnta6_over_err13woWrite-only0x0Enable for clk_check
mon6_err12woWrite-only0x0Enable for clk_check
cnta5_over_err11woWrite-only0x0Enable for clk_check
mon5_err10woWrite-only0x0Enable for clk_check
cnta4_over_err 9woWrite-only0x0Enable for clk_check
mon4_err 8woWrite-only0x0Enable for clk_check
cnta3_over_err 7woWrite-only0x0Enable for clk_check
mon3_err 6woWrite-only0x0Enable for clk_check
cnta2_over_err 5woWrite-only0x0Enable for clk_check
mon2_err 4woWrite-only0x0Enable for clk_check
cnta1_over_err 3woWrite-only0x0Enable for clk_check
mon1_err 2woWrite-only0x0Enable for clk_check
cnta0_over_err 1woWrite-only0x0Enable for clk_check
mon0_err 0woWrite-only0x0Enable for clk_check